Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-03-23
2002-06-18
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185110, C365S185300
Reexamination Certificate
active
06407944
ABSTRACT:
This application incorporates by reference an application for Method For Protecting An Over-erasure Of Redundant Memory Cells During Test For High-density Nonvolatile Memory Semiconductor Devices earlier filed in Korean Industrial Property Office on Dec. 31, 1997 and there duly assigned Ser. No. 97-81001.
FIELD OF THE INVENTION
The invention relates to nonvolatile semiconductor memory devices, and more particularly to a method for preventing over-erasure of redundant memory cells of nonvolatile semiconductor memories during test thereof.
BACKGROUND OF THE INVENTION
Flash memories perform data access operations, i.e., reading and writing (or programming) at high speed as compared to other kinds of nonvolatile memories such as electrically erasable and programmable read only memories. Because of its high speed operation, flash memory has been adapted to portable computing devices, cellular phones, digital still cameras, and so on.
Typical construction of a flash memory cell (or cell transistor) appropriate for either single-bit or multi-bit storage is shown in FIG.
1
. Source
3
and drain
4
, each being formed of an N+ diffused region in a P+ semiconductor substrate or bulk
2
, are separated from each other by a channel region (not numbered) in bulk
2
. Floating gate
6
is formed over the channel region, and separated from it by a thin (e.g., less than 100 Å thick) insulating film
7
. A second insulating film
9
, such as an O—N—O (Oxide—Nitride—Oxide) film, is formed on floating gate
6
to isolate control gate
8
from floating gate
6
. Source
3
, drain
4
, control gate
8
, and bulk
2
are each connected to their corresponding voltage sources Vs (source voltage), Vd (drain voltage), Vg (gate voltage) and Vb (bulk voltage), for programming, erasing, and reading operations.
A selected memory cell is programmed by means of hot electron injection between its channel region and its floating gate. During a programming operation, source and bulk are held at a ground voltage, a high voltage (e.g., 10V) is applied to a control gate, and a hot electron injection voltage (e.g., 5-6V) is provided to drain. After programming, a selected memory cell has an increased threshold voltage (e.g., to 6-7V) due to the deposition of electrons in the floating gate, as shown in FIG.
2
.
To read data from the programmed cell, a voltage of about 1V is applied to the drain, a power source voltage (e.g., about 4.5V) is applied to the control gate, and the source is held at the ground voltage. Since the increased threshold voltage of a programmed memory cell acts as a blocking potential against the gate voltage during a read-out operation, a programmed cell remains off during the read operation, while an erased cell turns on.
A memory cell is erased either by inducing F-N (Fowler-Nordheim) tunneling between its control gate and its source (hereinafter, this manner is referred to as a “source erasing”) or by inducing F-N tunneling between its control gate and its bulk (hereinafter, this manner is referred to as a “bulk erasing”).
In erase operations for most state-of-the-art flash memories, source regions (for source erasing) or bulk regions (for bulk erasing) of multiple memory cells are combined commonly, so that the memory cells can be spontaneously erased at the same time. The units of erasing (hereinafter referred to as a “sector”, for instance, one sector of, e.g., 16, 32, or 64 Kbytes) are determined in accordance with the number of separate source or bulk regions.
During such an erase operation of a memory cell, the control gate is coupled to a high negative voltage of about −10V, and source (for source erasing) or bulk (for bulk erasing) is held at a positive voltage of about 5V in order to induce tunneling therebetween. At the same time, drain and bulk (for source erasing), or drain and source (for bulk erasing) are conditioned at a high impedance state (or a floating state). Under these voltage bias conditions, a strong electric field is induced between the control gate and either the source or the bulk, and the electric field causes electrons to move from the floating gate into the source or the bulk. F-N tunneling normally occurs when an electric field in the range of 6-7 MV/cm is developed in the thin insulating film separating the floating gate and the source or bulk. An erased cell has a lower threshold voltage (e.g., 1-3V) than a programmed cell (e.g., 6-7V), as shown in
FIG. 2
, and is thereby sensed as an on-cell.
Generally, since source erasing creates a smaller coupling capacitance between channel and floating gate than bulk erasing does, the source erasing brings about fewer over-erased cells. The source erasing, however, not only consumes larger power than the bulk erasing but also causes faster deterioration of tunnel oxide, on account of band-to-band tunneling current and a larger number of hot electrons in sources. In addition, a cell in a source erasing architecture occupies a larger area than a cell in a bulk erasing architecture because the cell for source erasing needs an additional N-region for its source. Furthermore, as a cell for the source erasing has an F-N tunneling area smaller than the bulk erasing with advancement of cell scaling-down, the source erasing may have a drawback of causing a decrease in the uniformity of threshold voltage distribution. Accordingly, the bulk erasing architecture is suitable for high-density devices, rather than the source erasing architecture.
Meanwhile, a cell array of a flash memory device is typically divided into a main field for storing data and a redundant field for repairing defects in the main field. The redundant field contains multiple spare memory cells arranged to repair defective cells of the main field due to hard defects or soft defects. The spare cells are substituted for the defective memory cells, so that a defective device can develop into a non-defective one as a whole. A usual manner for repairing cell defects is determined by the architecture of the core region (typically, defect repair uses row redundancy or column redundancy).
After wafer manufacturing processes, a flash memory device requires a test procedure (including programming, program-verifying, erasing, and erase-verifying operations) to identify whether the device has defects. During such a test, a flash memory device is tested by programming main-field cells, in sequence, and then erasing them by applying negative voltages to their word lines. And, such programming and erasing cycles for device test are performed repeatedly.
With repetitive erasing for device test, one or more cells may be erased below a minimum acceptable threshold voltage (e.g., 1V), as shown in
FIG. 2. A
cell erased below the minimum threshold is commonly referred to as being “over-erased”. An over-erased cell acts “depletion-like” and induces a leakage current on its associated bit-line, thereby causing errors when other cells on the same bit-line are read.
Accordingly, over-erased cells need erasure correction to raise their thresholds by about 1V. One solution for this is to perform an iterative process utilizing over-erase verification and low-voltage level programming.
For instance, an operation for curing over-erase cells of a flash memory device with a column redundant architecture, during such a device test, can begin with selecting a row (i.e., a word-line) and examining cells on the selected row one by one along columns (i.e., bit-lines) to determine whether there are over-erased cells. This procedure is commonly referred to as over-erase verification. In this verify operation, a cell is identified as over-erased when it conducts current in excess of the current expected at the lowest threshold voltage (e.g., 1V). Once a cell is identified as over-erased, it is programmed with low-level curing voltages (e.g., 2-5 V to the control gate, 6-9 V to the drain, and 0 V to the source and bulk). Curing the remaining cells on other rows is performed in the same fashion.
When some main-field cells within a sector become over-erased with repetitive e
Choi Ki-Hwan
Park Jong-Min
Marger Johnson & Mccollom, P.C.
Phan Trong
Samsung Electronics Co,. Ltd.
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