Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-09-08
2008-08-19
Do, Thuan V. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07415692
ABSTRACT:
A programming method efficiently programs programmable logic devices of the type having specialized multiplier blocks that include multipliers and other arithmetic function elements. Such blocks can be used to perform certain multiplication and multiplication-related functions more efficiently than general-purpose programmable logic. In order to efficiently program devices having such specialized multiplier blocks, so that they are used to their full potential and so that the maximum number of multiplier-related functions can be accommodated on a single programmable logic device, the programming method pre-processes the netlist of function blocks in a user's programmable logic design, grouping multiplication and multiplication-related functions efficiently. The method takes into account limitations imposed by the structure of the specialized multiplier blocks, in addition to location constraints imposed by the user and location constraints dictated by the need for certain functions be carried out near where certain other functions are carried out.
REFERENCES:
patent: 5036473 (1991-07-01), Butts et al.
patent: 5043914 (1991-08-01), Nishiyama et al.
patent: 5197016 (1993-03-01), Sugimoto et al.
patent: 5287511 (1994-02-01), Robinson et al.
patent: 5296935 (1994-03-01), Bresler
patent: 5351206 (1994-09-01), Yang et al.
patent: 5524244 (1996-06-01), Robinson et al.
patent: 5530664 (1996-06-01), Tsubata et al.
patent: 5553001 (1996-09-01), Seidel et al.
patent: 5661660 (1997-08-01), Freidin
patent: 5815405 (1998-09-01), Baxter
patent: 5854929 (1998-12-01), Van Praet et al.
patent: 5867400 (1999-02-01), El-Ghoroury et al.
patent: 5892678 (1999-04-01), Tokunoh et al.
patent: 6094726 (2000-07-01), Gonion et al.
patent: 6134707 (2000-10-01), Herrmann et al.
patent: 6185724 (2001-02-01), Ochotta
patent: 6219628 (2001-04-01), Kodosky et al.
patent: 6223329 (2001-04-01), Ling et al.
patent: 6298319 (2001-10-01), Heile et al.
patent: 6298472 (2001-10-01), Phillips et al.
patent: 6360356 (2002-03-01), Eng
patent: 6367056 (2002-04-01), Lee
patent: 6477683 (2002-11-01), Killian et al.
patent: 6584601 (2003-06-01), Kodosky et al.
patent: 6785700 (2004-08-01), Masud et al.
patent: 6862563 (2005-03-01), Hakewill et al.
patent: 7051313 (2006-05-01), Betz et al.
patent: 7210112 (2007-04-01), DeHon et al.
patent: 2002/0069396 (2002-06-01), Bhattacharya et al.
patent: 2004/0015528 (2004-01-01), Langhammer et al.
patent: 2004/0098438 (2004-05-01), Chung
patent: 2004/0103265 (2004-05-01), Smith
Ahmed Elias
Bourgeault Mark
Farrugia Jennifer
Altera Corporation
Do Thuan V.
Ingerman Jeffrey H.
Levin Naum B
Ropes & Gray LLP
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