Method for programming and erasing an array of NMOS EEPROM...

Details Method for programming and erasing an array of NMOS EEPROM... Method for programming and erasing an array of NMOS EEPROM...

2008-12-10

2010-10-19

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185270, C365S185290

Reexamination Certificate

active

07817474

ABSTRACT:
A method for programming and erasing an array of NMOS electrically erasable programmable read only memory (EEPROM) cells that minimizes bit disturbances and high voltage requirements for the memory array cells and supporting circuits. In addition, the array of N-channel memory cells may be separated into independently programmable memory segments by creating multiple, electrically isolated P-wells upon which the memory segments are fabricated. The multiple, electrically isolated P-wells may be created, for example, by p-n junction isolation or dielectric isolation.

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