Method for programming and erasing an array of NMOS EEPROM...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C257S315000

Reexamination Certificate

active

07466591

ABSTRACT:
A method for programming and erasing an array of NMOS electrically erasable programmable read only memory (EEPROM) cells that minimizes bit disturbances and high voltage requirements for the memory array cells and supporting circuits. In addition, the array of N-channel memory cells may be separated into independently programmable memory segments by creating multiple, electrically isolated P-wells upon which the memory segments are fabricated. The multiple, electrically isolated P-wells may be created, for example, by p-n junction isolation or dielectric isolation.

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International Search Report and Written Opinion for PCT/US2007/069726 mailed Feb. 20, 2008.

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