Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2006-06-01
2008-12-16
Zarabian, Amir (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C257S315000
Reexamination Certificate
active
07466591
ABSTRACT:
A method for programming and erasing an array of NMOS electrically erasable programmable read only memory (EEPROM) cells that minimizes bit disturbances and high voltage requirements for the memory array cells and supporting circuits. In addition, the array of N-channel memory cells may be separated into independently programmable memory segments by creating multiple, electrically isolated P-wells upon which the memory segments are fabricated. The multiple, electrically isolated P-wells may be created, for example, by p-n junction isolation or dielectric isolation.
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International Search Report and Written Opinion for PCT/US2007/069726 mailed Feb. 20, 2008.
Gerber Donald
Hewitt Kent
Shields Jeffrey A.
Baker & Botts L.L.P.
Lappas Jason
Microchip Technology Incorporated
Zarabian Amir
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