Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-01-04
2002-12-10
Potter, Roy (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S648000, C438S683000
Reexamination Certificate
active
06492253
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to integrated circuit packages, and more particularly to a programmable substrate design that is used for array-type packages including Ball Grid Arrays (BGA), Pin Grid Arrays (PGA) and Column Grid Arrays (CGA).
In the last few decades, the electronics industry has literally transformed the world. Electronic products are used by, or affect the daily lives of, a large segment of the world's population. For example, telephones, television, radios, Personal Computers (PCs), laptop PCs, palmtop PCs, PCs with built-in portable phones, cellular phones, wireless phones, pagers, modems, and video camcorders, are just a few of the electronic products that have been developed in recent years and which have been made smaller and more compact, while providing more and/or enhanced functions than ever before. The integrated circuit (IC) chip or IC die, and the more efficient packaging of the IC chip, have played a key role in the success of these products.
The IC chip is not an isolated island. It must communicate with other chips in a circuit through an Input/Output (I/O) system of interconnects. Moreover, the IC chip and its embedded circuitry are delicate, and must therefore be protected in a package that can both carry and protect it. As a result, the major functions of the IC package are: (1) to provide a path for the electrical current that powers the circuits on the chip; (2) to distribute the signals on to and off of the chip; (3) to remove the heat generated by the circuit; and (4) to support and protect the chip from hostile environments.
Integrated circuits are typically housed within a package that is mounted to a printed circuit board (PCB). The package has conductive leads or pins that are soldered to the PCB and coupled to the integrated circuit by a lead frame. In array type packages, the substrate is designed with predetermined interconnections between the bond pad of the IC die or IC chip and the array connection, either a ball, pin or column. The substrates are generally ceramic or plastic based. The circuitry for the connection between the pad and ball are formed by photo etching for plastic laminate base material or screened-on conductive material for ceramic based materials.
FIG. 1
shows the prior art structure of an integrated circuit (IC)
100
. The IC
100
is made from a base substrate
110
that includes a central or inner section on the top surface wherein an integrated circuit (IC) die
115
is located. The IC die
115
is secured to the base substrate
110
. Around the periphery of the IC die
115
are IC contact pads
120
.
Located within the base substrate
110
are a spaced array of metallically line vias
125
. As is known in the art, a via is made by drilling a hole through the substrate and then plating or lining the hole with a conductive material such as copper, gold or silver. Located on the top surface of the base substrate
110
are a plurality of conductive traces
130
. The traces
130
extend radially out from the IC die
115
and the termination of each trace
130
is to an individual via
125
. The inner end of each trace
130
is a bonding pad
140
, near the IC die
115
. The bonding pad
140
is electrically joined to the contact pads
120
with bonding wires
135
. On the bottom surface of the base substrate
110
, the via
125
may be connected to solder balls to form a Ball Grid Array (BGA) package, or connected to pins to form a Pin Grid Array (PGA) package, or connected to columns to form a Column Grid Array (CGA) package.
Each device manufacturer typically has preferred integrated circuit designs. In current practice, the substrate is typically optimized for a particular integrated circuit design, with the appropriate die-to-ball, die-to-pin or die-to-column connections (hereafter “pad-to-pin” connections) being included in the design for the best performance of the device. The substrate has to be designed, tooled and manufactured before the IC die can be packaged. Additionally, each new IC requirement mandates a new substrate design and tooling to manufacture.
After the substrate is designed, changes cannot be made without re-designing and re-tooling. This generally takes weeks. The IC die designer can use existing substrates, but since the pad-to-pin connection is set, the IC die function may not be optimum. A fixed substrate design does not allow the IC die designer to evaluate the different options for optimized performance without going to multiple designs and long fabrication cycle times. Moreover, any errors in the design require retooling of the substrate to correct.
In certain situations, there is a need to connect a certain pad on the IC die to a particular array location. For example, a specific pad-to-pin connection may be needed to improve the performance of the device. Unfortunately, a specific pad-to-pin connection typically means a custom design of the substrate, which is costly and takes time to implement.
While it is known in the art for an assembly manufacturer to service different customers with different IC die connections, this requires that the manufacturer design and stock different substrates for each of the different IC dies that are to be used by its customers. Disadvantageously, such multi-substrate-design and stocking can be expensive.
In view of the above, it is evident that what is needed is a substrate that can be programmed or easily reused or modified by the assembly manufacturer so as to allow pad-to-pin connections to be modified to facilitate different IC die connections, reduce the fabrication cycle time for new designs and to thereby make the design and implementations of different IC packages more cost effective.
SUMMARY OF THE INVENTION
The present invention addresses the above and other needs by providing a programmable substrate for array-type packages and a method of making the programmable substrate that improves the compatibility of the substrate with a wide variety of integrated circuit dies. Advantageously, such programmable substrate and method dramatically reduces the time to develop and market custom IC package designs.
While prior art substrates have traces that start from the IC die and end at the via, the present invention provides traces that also start at the IC die but go past the via, and in fact go past several vias, all the way to the perimeter of the substrate. The present invention allows the traces to be connected to any one of the nearby vias, while the prior art teaches that each trace must be connected to a particular via, thus fixing the design.
The programmable substrate described herein can be used with many kinds of array type packages, including Ball Grid Array (BGA) packages, Pin Grid Array (PGA) packages and Column Grid Array (CGA) packages. Basically, the programmable substrate of the present invention includes a nonconductive programmable substrate having a cavity therein (or a surface thereon) sized to receive an integrated circuit die. An array of electrically conductive vias pass through the substrate to make contact with each pin, ball, or column on the bottom of the package. A plurality of electrical traces on the top of the substrate extend from an edge of the cavity to the periphery of the substrate, passing between and near the vias. Each trace is connected at its edge-of-cavity end to a pad on the die using conventional wire-bonding techniques. Each trace may then also be selectively connected to a desired pin, ball, or column by connecting a wire bond between the via corresponding to the desired pin, ball, or column and the trace as the trace passes near the via. Thus, by selectively connecting the traces to vias corresponding to desired pins, balls, or columns, the pad-to-pin connections of the IC package may be programmed.
REFERENCES:
patent: 4688152 (1987-08-01), Chia
patent: 4778641 (1988-10-01), Chia
patent: 4972253 (1990-11-01), Palino et al.
patent: 5400220 (1995-03-01), Swamy
patent: 5434750 (1995-07-01), Rostoker et al.
patent: 5435482 (1995-07-01), Variot et al.
patent: 5563446
Chia Chok J.
Lim Seng-Sooi
Variot Patrick
LSI Logic Corporation
Potter Roy
LandOfFree
Method for programming a substrate for array-type packages does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for programming a substrate for array-type packages, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for programming a substrate for array-type packages will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2992868