Method for programming a programmable gate array having shared s

Details Method for programming a programmable gate array having shared s Method for programming a programmable gate array having shared s

1999-03-16

2000-03-14

Santamauro, Jon

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

326 41, H03K 19177

Patent

active

06037800&

ABSTRACT:
A method for using shared signal lines for interconnection of logic elements and configuration of a programmable gate array. A signal line which is shared for purposes of interconnection and configuration saves chip space. During configuration, a shared signal line is used to route configuration bits to configuration memory cells, and during operation of the programmable gate array, the shared signal line is used to interconnect logic elements of the programmable gate array.

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patent: 5909125 (1999-06-01), Kean
Xilinx, Inc. "The Programmable Logic Data Book," Sep. 1996, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124.
Betty Prince, "Semiconductor Memories," copyright 1983, 1991, John Wiley & Sons, pp. 149-174.
Anthony Stansfield, et al., "The Design of a New FPGA Architecture," 1995, Computer Science 975.

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