Static information storage and retrieval – Floating gate – Disturbance control
Patent
1998-12-28
2000-05-09
Tran, Andrew Q.
Static information storage and retrieval
Floating gate
Disturbance control
36518517, 36518519, G11C 1604
Patent
active
060612703
ABSTRACT:
There is provided a non-volatile memory device programming method for improving soft programming. In the programming method, a first voltage for program inhibition is applied to a bit line, and a second voltage is applied to the gate of a first select transistor, unselected word lines, and a selected word line. Then, after blocking a current path, a third voltage is applied to the word line of a first unselected memory cell and the word line of a second unselected memory cell sharing the drain and the source of a memory cell on the selected word line in order to decouple the first and second unselected memory cells from the other unselected memory cells. A fourth voltage is applied to the unselected word lines except for the first and second unselected memory cells, thereby coupling the sources or drains of the first and second unselected memory cells and disconnecting the channel of the selected memory cell from those of the other unselected memory cells. Then, a program voltage is applied to the selected word line.
REFERENCES:
patent: 5715194 (1998-02-01), Hu
patent: 5898615 (1999-04-01), Chida
Suh, Kang-Deog, et al., "A 3.3 V 32Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme," IEEE Journal of Solid-State Circuits, vol. 30, No. 11, Nov. 1995, pp. 1149-1156.
Jung, Tae-Sung, et al., "A 3.3V 128Mb Multi-Level NAND Flash Memory for Mass Storage Applications," IEEE International Solid-State Circuits Conference, First Edition, Feb. 1996, pp. 32-33, 412.
Tomoharu, Tanaka, "A 4-Mbit NAND-EEPROM with Tight Programmed Vt Distribution," 1990 Symposium on VLSI Circuits, pp. 105-106.
Samsung Electronics Co,. Ltd.
Tran Andrew Q.
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