Method for production of semiconductor device

Details Method for production of semiconductor device Method for production of semiconductor device

2000-05-26

2001-10-23

Quach, T. N. (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S646000, C438S650000, C438S687000

Reexamination Certificate

active

06306756

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method for the production of a semiconductor device having electrode lines formed on a semiconductor substrate and more particularly to a method for the production of a semiconductor device provided with highly reliable interconnections and adapted for a Si semiconductor device or a compound semiconductor device.
2. Description of the Related Art
In recent years, the semiconductor devices such as, for example, integrated circuit devices (integrated circuit elements) represented by logic devices have been showing a conspicuous growth in the degree of integration. In consequence of this growing degree of integration, the lines to be used for electrically connecting active elements in such semiconductor devices are naturally expected to have line width decreased to the fullest possible extent. Since these fine lines are required to have high current density and high operating temperature as well, the practice of endowing the semiconductor devices with exalted reliability by forming these lines with a material of highly endurance against electromigration is in vogue.
While the semiconductor devices of this class are required to attain growth also in operating speed, the RC delay poses a serious problem on the way to the growth of operating speed. For the solution of this problem of the RC delay, it is essential that the passivation films be allowed a decrease in dielectric constant and the line materials be given a decrease in electrical resistance. As line materials which meet these requirements, Al or Al alloys, and Cu and Ag which have lower electric resistance than Al and higher activation energy for diffusion than Al have been known to the art.
As means of fabrication for producing fine electrode lines, generally the reactive ion etching (RIE) method and the ion milling method have been known. The Al lines, for example, is at a disadvantage in entraining the problem of suffering the lithography used in the process of fabrication to induce the phenomenon of exudation due to the reflection of light and the problem of disrupting the uniformity of fabrication owing to the precipitation and the presence of grain boundaries in the RIE process. These problems give rise to such inconveniences as impairing the shape of lines and degrading the reliability of interconnections.
Then, in the case of the Cu interconnections, the fabrication thereof as by the RIE method, for example, cannot be easily implemented because the chloride or fluoride of Cu has low vapor pressure. Specifically, an effort to increase the temperature of the semiconducting substrate as a subject matter of fabrication and increase the vapor pressure of the chloride or fluoride results in promoting the reaction of forming a chloride or fluoride to a point where this reaction affects the interior of the lines. Since no existing resist material is capable of withstanding high temperature, the electrode line still defies this fabrication for a decrease line width.
The method of physical fabrication by ion milling entrains the problem of encountering difficulty in the separation and removal of the masking material after fabrication due to ion damage and the problem of readily inducing a short circuit in the electrode line due to re-adhering of atoms removed by iron milling.
In recent years, for the fabrication of wiring in the process for production of the semiconductor devices mentioned above, the interconnect method resorting to the damascene process has been attracting attention and has been forming a mainstream in the fabrication under discussion. Specifically, the chemical mechanical polishing (CMP) technique has advanced to a point where electrode lines can be formed as required in an embedded pattern. Thus, the practice of forming the electrode lines with Al and Cu as the material is now prevailing. According to this method, an insulating film (interlayer film) is formed on a semiconducting substrate provided with an active region such as, for example, the active-region-forming surface of a Si substrate prior to the deposition of metal film and then trenches are preparatorily formed in the region of the insulating film expected to form the electrode lines.
Then, on the surface which has been fabricated to contain the trenches therein, a metal as the material for electrode line is deposited by the ordinary technique of sputtering, collimation sputtering (anisotropic sputtering), or CVD. Thereafter, by a heat treatment, the metal film deposited as described above is caused to flow and fill the trenches and metal film on the space is removed by CMP to complete the formation of electrode lines as required.
In this case, the connections to the active parts or to the electrodes in the lower layers are attained with metallic pieces which are either passed through contact holes formed in the insulating film or embedded in the insulating film during the formation of interconnections. Further, prior to the formation of a metal film for electrode lines, a barrier metal layer is generally formed.
Incidentally, the heat treatment which is intended for flowing the matal film and filling the trenches is carried out (1) subsequently to the formation of the metallic film with the relevant site kept under a high degree of vacuum, (2) under a degree of vacuum below the equilibrium dissociation pressure of an oxide where the site of formation of a Cu or Al film has been exposed once to the atmospheric exposure after the film deposition or in a stream of hydrogen gas after the chamber for the heat-treatment has been evacuated to a high degree of vacuum, or (3) in a forming gas (mixed gas of N
2
and H
2
generally having a H
2
concentration in the range of from 10 to 20%) of high purity where the heat treatment is to be carried out under an atmospheric pressure.
In any case, the heat treatment is carried out in an atmosphere deprived of an oxidizing gas to the fullest possible extent or in an atmosphere of reducing gas.
The heat treatment for the flow is confronted by two problems.
Firstly, as shown schematically in
FIG. 25A
, generally a metal film is deposited in a thickness amount 1.5 to 2.0 times the depth of trenches
1
for the purpose of increasing the initial amount of accumulation in the trenches
1
, for example. During the process of a heat treatment for flow, therefore, the surfaces of the opposed portions of the deposited film (metal film)
3
b
on the wall defiling a space
2
a
of the trench
1
contact each other and produce a bridge
3
a
and, as schematically shown in
FIG. 25B
, give rise to a void
4
within the trench
1
, with the result that the void
4
will persist and obstruct the flow. In the diagram,
2
and
5
each stand for an insulating film made of such a substance as SiO
2
or SiN, for example.
To be more specific about this point, when the metal intended for the interconnect is deposited by a physical vapor deposition, such as sputtering or vapor deposition, since the directions in which the hurled particles impinge on a substrate constitute a cosine distribution, the accumulation of deposited particles on the space
2
a
between the adjacent trenches
1
grows in the directions of the trenches
1
with the obliquely impinging particles and induce the occurrence of a overhung portion
3
b
which will obstruct the accumulation of particles inside the trench
1
. When the heat treatment is carried out in the presence of the overhung portion
3
b
which has grown as described above, the adjacent overhung portions
3
b
are suffered to contact each other in consequence of thermal expansion and the portions of this contact continuously grow (necking) to induce formation of a bridge
3
a
between the opposed walls of the space
2
a.
In consequence of the advance of the linkage between the opposed walls of the spaces
2
a,
the initial empty space remains beneath the region. Since this void
4
cannot be filled by an ordinary heat treatment, the interconnection which is subsequently formed by the CMP is destined to suffer vo

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