Method for producing tiered gate structure devices

Semiconductor device manufacturing: process – Forming schottky junction – Compound semiconductor

Reexamination Certificate

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C438S579000, C257SE21205

Reexamination Certificate

active

07439166

ABSTRACT:
In one implementation, a method for fabricating a tiered structure is provided, which includes forming a source and a drain on a substrate with a gate formed therebetween. Formation of the gate includes depositing a gate foot using a gate foot mask having an opening through it to define the gate foot over the substrate. After forming the gate foot, the gate foot mask is stripped. A gate head mask is formed over the gate foot with the gate head mask exposing a top portion of the gate foot. A gate head is formed on the top portion of the gate foot using the gate head mask. A lift-off process is performed, removing the gate head mask.

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R. Grundbacher, I. Adesida, Y.-C. Kao, A.A. Ketterson, Single step lithography for double-recessed gate pseudomorphic high electron mobility transistors, J. Vac. Sci. Technol. B 15 (1), pp. 49-52, American Vacuum Society, Jan./Feb. 1997.

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