Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Patent
1995-09-19
1997-11-11
Powell, William
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
438459, 438938, H01L 2100
Patent
active
056863640
ABSTRACT:
A method for producing for a SOI type bonded substrate for semiconductor integrated circuits which has a void areal ratio which approaches or is equal to zero %, when heat treated at temperatures on the order of 1250.degree. C. The method involves: superimposing a Si single crystal wafer having a main surface of which is covered by a Si polycrystal layer, beneath which Si single crystal islands are formed on the main surface and are isolated from each other by V grooves with interposition of a dielectric film, which V grooves are filled up by the Si polycrystal layer, and a support made from Si material between the Si polycrystal layer and a surface of the support with a dielectrically insulating layer sandwiched therebetween; and conducting heat treatment of the superimposed Si single crystal wafer and the support to effect bonding therebetween. According to the method any P-V value of recesses between the Si single crystal islands and the V grooves which are formed on the bonding surface of the Si polycrystal layer are set at 13 nm/250.times.250 .mu.m.sup.2 or less; and the heat treatment is conducted at a temperature in the range of 1100.degree. C. to 1250.degree. C.
REFERENCES:
patent: 4851078 (1989-07-01), Short et al.
Kanai Akio
Ohki Konomu
Tanaka Shinji
Powell William
Shin-Etsu Handotai & Co., Ltd.
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