Etching a substrate: processes – Gas phase etching of substrate – Application of energy to the gaseous etchant or to the...
Reexamination Certificate
1998-09-08
2001-04-03
Jones, Deborah (Department: 1775)
Etching a substrate: processes
Gas phase etching of substrate
Application of energy to the gaseous etchant or to the...
C216S067000, C216S069000, C216S046000, C438S668000, C438S696000, C438S710000, C438S712000, C438S720000, C438S732000, C428S469000, C428S697000
Reexamination Certificate
active
06210595
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a method for producing structures having a high aspect ratio, as well as to structures having a high aspect ratio.
During the last 25 years, the storage density of DRAM memory chips has quadrupled from one generation to the next. However, the fundamental structure of an elementary memory cell as well as the materials used to construct the memory cell have remained essentially unchanged during that time. Just like 25 years ago, a DRAM memory cell includes a transistor and a capacitor which stores the charge necessary to represent the information. The capacitor of the memory cell has electrodes made of doped silicon and/or polysilicon and a dielectric layer made of silicon dioxide and/or silicon nitride disposed between the electrodes.
In order to ensure that the charge stored in a capacitor may be read out in a reproducible manner, the capacitance of the capacitor should have at least a value of about 30 fF. At the same time, the lateral extent of the capacitor has had and is having to be continually reduced in size in order to be able to achieve the aforementioned increase in the storage density. Those inherently contrasting requirements of the capacitor of the memory cell have led and are leading to ever more complex structuring of the capacitor (“trench capacitors”, “stacked capacitors”, “crown-shaped capacitors”) in order to be able to provide a sufficient capacitor area despite the lateral extent of the capacitor becoming smaller. Accordingly, however, production of the capacitor becomes more and more complicated and thus more and more expensive.
Another way of ensuring that the capacitor has a sufficient capacitance is to use different materials between the capacitor electrodes. Recently, therefore, the conventional silicon oxide/silicon nitride has been replaced by the use of new materials, in particular paraelectrics and ferroelectrics, between the capacitor electrodes of a memory cell. Those new materials have a distinctly higher relative permittivity (>20) than the conventional silicon oxide/silicon nitride (<8). That means that given the same capacitance and the same lateral extent of the memory cell, the requisite capacitor area and thus the requisite complexity of the structuring of the capacitor can be distinctly reduced by the use of those materials. Barium strontium titanate (BST, (Ba,Sr)TiO
3
), lead zirkonate titanate (PZT, Pb(Zr,Ti)O
3
) and lanthanum-doped lead zirkonate titanate or strontium bismuth tantalate (SBT, SrBi
2
Ta
2
O
9
) are used, for example.
Unfortunately, using the new paraelectrics or ferroelectrics also means using new electrode materials. The new paraelectrics or ferroelectrics are usually deposited onto existing electrodes (bottom electrodes). Processing takes place at high temperatures. The materials of which the capacitor electrodes are normally composed, thus e.g. doped polysilicon, are easily oxidized and lose their electrically conductive properties at those temperatures, which would lead to failure of the memory cell.
Due to their good oxidation resistance and/or the formation of electrically conductive oxides,
4
d
and
5
d
transition metals, in particular platinum metals (Ru, Rh, Pd, Os, Ir, Pt) and particularly platinum itself, as well as rhenium, are promising candidates that might replace doped silicon/polysilicon as electrode material.
However, if a simply structured “stacked capacitor” suffices to provide the requisite capacitance, when the new materials (e.g. platinum and BST) are used for the first time, the unabating miniaturization of the memory cell in further DRAM generations means that the capacitors composed of the new materials must also be structured correspondingly more complexly in order to ensure a sufficient capacitor area. Large surfaces in conjunction with a small lateral extent can only be obtained, as a rule, through the use of structures having a large aspect ratio (ratio of height to width). However, it is precisely structures of that type that cannot be produced, or can be produced only with a high outlay, using the new paraelectrics or ferroelectrics and the new electrode materials.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for producing structures having a high aspect ratio, in particular from the above-mentioned materials, as well as a structure having a high aspect ratio, which overcome the hereinafore-mentioned disadvantages of the heretofore-known methods and devices of this general type.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for producing structures having a high aspect ratio, which comprises providing a material of a structure to be produced, in the form of a layer; applying a mask with side walls to the layer; subjecting the layer to dry etching using the mask and forming redepositions of the layer material on the side walls of the mask; removing the mask and leaving behind a structure having a high aspect ratio.
The method according to the invention enables very high (≧1 &mgr;m) and very thin (≦50 nm) structures to be produced in a relatively simple and rapid manner in only very few process steps and with only one mask technique. Structures having such large aspect ratios, particularly when they are composed of a conductive material, cannot be produced, or can be produced only with a high outlay, by using other methods.
In accordance with another mode of the invention, a plasma etching process is used for the dry etching of the layer.
In accordance with a further mode of the invention, during the dry etching of the layer, a gas or gas mixture, preferably a noble gas, is provided which does not form volatile compounds with the material of the structure to be produced.
In accordance with an added mode of the invention, a number of processes can be used for the dry etching of the layer. Reactive ion etching (RIE), magnetically enhanced reactive ion etching (MERIE), electron cyclotron resonance etching (ECR etching) or inductively coupled plasma etching processes (ICP, TCP) are preferably used for the dry etching of the layer.
In accordance with an additional mode of the invention, the aspect ratio of the structure is greater than 2, preferably greater than 10, in particular greater than 20.
In accordance with yet another mode of the invention, the structure is constructed to be a self-stabilizing structure.
In accordance with yet a further mode of the invention, the structure is constructed to be a closed structure, for example a closed ring.
In accordance with yet an added mode of the invention, a multiplicity of materials may be used. Preferably, however, the layer contains a metal, in particular copper, iron, cobalt, nickel, or a
4
d
or
5
d
transition metal, in particular a platinum metal.
In accordance with yet an additional mode of the invention, the layer contains platinum, gold, silver, iridium, palladium, ruthenium, rhenium or oxides thereof.
In accordance with again another mode of the invention, there is provided at least one further layer applied to the structure, again resulting in a structure having a high aspect ratio.
In accordance with again a further mode of the invention, the further layer is an insulation layer.
In accordance with again an added mode of the invention, the further layer contains a ferroelectric material, a dielectric material, in particular a dielectric material having high relative permittivity, a perovskite or precursors of these materials. In this case, a precursor of the above-mentioned materials is to be understood to mean a material which can be converted into the above-mentioned materials through the use of suitable heat treatment (e.g. annealing), if appropriate with oxygen being fed in.
In accordance with again an additional mode of the invention, the further layer contains strontium bismuth tantalate (SBT, SrBi
2
Ta
2
O
9
), strontium bismuth niobate tantalate (SBNT, SrBi
2
Ta
2−x
Nb
x
O
9
, x=0-2) or derivatives, lead zirkon
Engelhardt Manfred
Weinrich Volker
Greenberg Laurence A.
Infineon - Technologies AG
Jones Deborah
Lerner Herbert L.
Stein Stephen
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