Single-crystal – oriented-crystal – and epitaxy growth processes; – Processes of growth with a subsequent step of heat treating...
Reexamination Certificate
2000-04-20
2002-07-02
Kunemund, Robert (Department: 1765)
Single-crystal, oriented-crystal, and epitaxy growth processes;
Processes of growth with a subsequent step of heat treating...
C117S906000, C428S641000
Reexamination Certificate
active
06413310
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method for producing a silicon single crystal wafer with very few crystal defects on the surface and near the surface of the wafer, and a silicon single crystal wafer.
BACKGROUND ART
As wafers for producing devices such as semiconductor integrated circuits, CZ silicon single crystal wafers grown by the Czochralski method (CZ method) have been mainly used. If crystal defects are present in such CZ silicon single crystal wafers, pattern failure and the like will be caused during the semiconductor device production. In particular, since the pattern width required for the recent highly integrated devices has become extremely fine, i.e., 0.3 &mgr;m or less, even the presence of defects of 0.1 &mgr;m size may cause pattern failure at the time of such pattern formation, and it markedly reduces production yield of devices and degrades quality characteristics of devices. Therefore, the size of crystal defects present in silicon single crystal wafers must be made small as much as possible.
Recently, in particular, it has been reported that, in silicon single crystals grown by the CZ method, crystal defects called grown-in defects introduced during the crystal growth are detected by various measurement methods. For example, in commercially produced single crystals pulled at a usual growth rate (for example, about 1 mm/min or higher), they can be detected by using a commercially available particle counter (for example, SP1 produced by KLA/Tencor Co., Ltd.) as crystal originated particles (COP).
The cause of the generation of such crystal defects is considered to be clusters of atomic holes aggregated during the production of single crystals or oxide precipitates which are aggregates of oxygen atoms introduced from quartz crucibles. If these crystal defects exist in surface layers (0-5 &mgr;m) of wafers in which devices are formed, they act as harmful defects degrading the device characteristics. Therefore, there have been investigated various methods for reducing such crystal defects.
For example, it has been known that, in order to reduce the density of the aforementioned atomic hole clusters, crystals can be grown at an extremely reduced crystal growth rate (for example, 0.45 mm/min or lower, see Japanese Patent Application Laid-open (Kokai) No. 8-330316). In this method, however, crystal defects considered to be dislocation loops formed by aggregated excessive interstitial silicon are newly generated, and markedly degrade the device characteristics. Thus, it has become clear that the method cannot be a solution of the problem. Moreover, since the method uses a crystal growth rate reduced from the conventional rate of about 1.0 mm/min to 0.4 mm/min or lower, it markedly reduces the productivity of single crystals and increases the cost.
Further, as another method, there has also been proposed a method comprising a heat treatment of wafers grown at a commercially used usual conventional crystal growth rate of about 1.0 mm/min or higher in a hydrogen atmosphere to eliminate the grown-in defects, and it is used for the actual production. However, it has been pointed out that this method sill leaves the defects in surface layers (0-5 &mgr;m from the surfaces).
Furthermore, in the aforementioned method, it is necessary to secure safety after the heat treatment in a hydrogen atmosphere by replacing the atmosphere in the heat treatment furnace with nitrogen gas and then taking out the wafers. However, a small amount of oxygen and moisture contained in the nitrogen gas may locally etch the wafer surfaces, and thus the method also suffers from a problem that surface roughness such as haze and microroughness may be degraded.
The term “haze” used herein means periodical surface roughness having a period of several to several tens of nanometers on the wafer surfaces, and it can be determined semi-quantitatively by scanning whole surfaces of wafers with a particle counter mainly utilizing a laser, and measuring intensity of scattered reflection thereof.
On the other hand, microroughness is surface roughness evaluated as a P−V (peak to valley) value or RMS (root mean square roughness) value in a fine area (e.g., 2 &mgr;m square), which are obtained by investigating the area with an atomic force microscope.
DISCLOSURE OF THE INVENTION
The present invention has been accomplished in view of the aforementioned problems, and its major object is to obtain silicon single crystal wafers for semiconductor devices of high quality from a silicon single crystal ingot produced by the CZ method with high productivity. In the silicon single crystal wafers, grown-in defects in their surface layers are effectively reduced or eliminated, and the wafers are also excellent in the wafer surface roughness.
In order to achieve the aforementioned object, the present invention provides a method for producing a silicon single crystal wafer, which comprises growing a silicon single crystal ingot by the Czochralski method, slicing the single crystal ingot into a wafer, subjecting the wafer to a heat treatment at a temperature of 1100-1300° C. for 1 minute or more under a non-oxidative atmosphere, and successively subjecting the wafer to a heat treatment at a temperature of 700-1300° C. for 1 minute or more under an oxidative atmosphere without cooling the wafer to a temperature lower than 700° C.
By the aforementioned method for producing a silicon single crystal wafer, which comprises growing a silicon single crystal ingot by the Czochralski method, slicing the single crystal ingot into a wafer, subjecting the wafer to a heat treatment at a temperature of 1100-1300° C. for 1 minute or more under a non-oxidative atmosphere, and successively subjecting the wafer to a heat treatment at a temperature of 700-1300° C. for 1 minute or more under an oxidative atmosphere without cooling the wafer to a temperature lower than 700° C., grown-in defects in the wafer surface layer, which are harmful to the semiconductor device production, can be eliminated or reduced within a short period of time. Simultaneously, a silicon single crystal wafer for semiconductor devices of high quality excellent in the wafer surface roughness can be obtained with high productivity.
In the aforementioned method, the non-oxidative atmosphere is preferably argon, nitrogen or a mixed gas of argon and nitrogen.
This is because argon, nitrogen or a mixed gas of argon and nitrogen has an advantage that it is easy to be handled and inexpensive.
In the aforementioned method, the oxidative atmosphere may be an atmosphere containing water vapor.
By using an atmosphere containing water vapor as the oxidative atmosphere as mentioned above, a high oxidation rate can be obtained, and thus interstitial silicon can efficiently be injected within an extremely short period of time to eliminate the defects. In addition, since the oxide film formed on the surface becomes relatively thick, it is suitable for applications in which the oxide film is used as it is in the wafer processing process or the device production.
In the aforementioned method, the oxidative atmosphere may also be a dry oxygen atmosphere or a mixed gas atmosphere of dry oxygen and argon or nitrogen.
By using a dry oxygen atmosphere or a mixed gas atmosphere of dry oxygen and argon or nitrogen as the oxidative atmosphere as mentioned above, a slow growth rate of the oxide film can be obtained, and thus the oxide film formed on the surface after the heat treatment can be made thin. Therefore, when the formed oxide film must be eliminated with an aqueous solution of HF or the like, the time required for this step can be shortened.
Thickness of an oxide film formed by the heat treatment under the oxidative atmosphere is preferably controlled to be 20-100 nm.
If the thickness of the oxide film formed by the heat treatment under the oxidative atmosphere is 20 nm or more, COPs in the wafer surface layer can sufficiently be eliminated. If it is 100 nm or less, even when the formed oxide film must be eliminated, time required for that step can be shortened.
More
Akiyama Shoji
Kobayashi Norihiro
Shinomiya Masaru
Tamatsuka Masaro
Anderson Matthew A
Kunemund Robert
Oliff & Berridg,e PLC
Shin-Etsu Handotai & Co., Ltd.
LandOfFree
Method for producing silicon single crystal wafer and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for producing silicon single crystal wafer and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for producing silicon single crystal wafer and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2889920