Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2007-08-07
2007-08-07
Smoot, Stephen W. (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S656000, C438S686000, C438S687000, C257SE21584
Reexamination Certificate
active
11392540
ABSTRACT:
Provided is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semiconductor substrate that the neighboring film is contacted with the conductor film. In the device, the materials for the conductor film and the neighboring film are so selected that the difference between the short side, ap, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the short side, an, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {|ap−an|/ap}×100=A (%) and the difference between the long side, bp, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the long side, bn, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {|bp−bn|/bp}×100=B (%) satisfy an inequality of {A+B×(ap/bp)}<13. In this, the diffusion of the conductor film is retarded.
REFERENCES:
patent: 4851895 (1989-07-01), Green et al.
patent: 5510651 (1996-04-01), Manier et al.
patent: 5674787 (1997-10-01), Zhao et al.
patent: 5824599 (1998-10-01), Schacham-Diamand et al.
patent: 6020266 (2000-02-01), Hussein et al.
patent: 6054331 (2000-04-01), Woo et al.
patent: 2002/0006468 (2002-01-01), Paranjpe et al.
patent: 05-315336 (1993-11-01), None
patent: 6-236878 (1994-08-01), None
patent: 09-069522 (1997-03-01), None
patent: 10-022274 (1998-01-01), None
patent: 10-229084 (1998-08-01), None
patent: 10-256251 (1998-09-01), None
patent: 10-284601 (1998-10-01), None
“In-Situ Barrier Layer and Metallization Via CVD,” IBM Technical Disclosure Bulletin vol. 34, No. 7B, p. 246 (Dec. 1991).
“Diffusion Barrier Between Copper and Silicon”, IBM Technical Disclosure Bulletin, vol. 35, No. 1B, pp. 214-215, Jun. 1992.
JP 2001-505367 (machine translation only).
Iwasaki Tomio
Miura Hideo
Antonelli, Terry Stout & Kraus, LLP.
Smoot Stephen W.
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