Method for producing PMOS devices

Details Method for producing PMOS devices Method for producing PMOS devices

1999-06-25

2001-03-13

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

C438S302000, C438S303000

Reexamination Certificate

active

06200840

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method for producing PMOS devices, and more particularly to a method for preventing boron segregation and out diffusion for producing PMOS devices.
2. Description of the Prior Art
Continuous expansion of integrated circuit density requires chip area to remain the same or even become smaller in order to reduce circuit unit cost incessantly, and the only solution to this is an endless diminishment of the design rules. Moreover, once devices shrink in size, the degree of shrinkage in gate sizes is even greater than for other design rules, and it is mainly because of the taking of the fact of device efficiency into consideration. The junctions of source/drain regions must be shallow to avoid short channel effect when devices shrink in size. Therefore, boron ions (boron or boron fluoride) with low energy and high dosage must be used, and shallow junctions of PMOS devices are formed by carrying out ion implantation. But thermal diffusion might occur inside the silicon wafer that is caused by the implanted boron ions during a follow-up annealing process. This results in low resistivity source/drain regions and high driving current because the boron ion density closest to the wafer's surface is decreased, furthermore, semiconductor device performance is worsened.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for forming PMOS devices that substantially prevents boron segregation and out diffusion.
It is an object of the present invention to provide a method to prevent boron segregation and out diffusion for producing PMOS devices, because a thin nitride oxide (NO, N
2
O) layer is formed by using rapid thermal oxidation (RTO) and rapid thermal nitridation (RTN) in the present invention. Although a crystallized structure on the silicon wafer's surface can be recovered during a follow-up annealing process, thermal diffusion might occur inside the silicon wafer that is caused by the implanted boron ions. Hence, the boron ion density closest to the wafer's surface will be decreased. By means of the formation of this thin nitride oxide (NO, N
2
O) layer, reduction of boron ion density close to the surfaces of source/drain regions due to boron segregation to TEOS liner oxide layer and out diffusion can be effectively prevented during the annealing process. Therefore, the boron ion density closest to the wafer's surface can be maintained.
It is another object of the present invention to provide a method producing PMOS devices which with low resistivity source/drain regions and high driving current by a thin nitride oxide (NO, N
2
O) layer formed by using rapid thermal oxidation (RTO) and rapid thermal nitridation (RTN). Moreover, during a follow-up annealing process, thermal diffusion might occur inside the silicon wafer that is caused by the implanted boron ions. Hence, the boron ion density close to the wafer's surface will be decreased and end up with higher resistivity and lower driving current. By means of the formation of this thin nitride oxide (NO, N
2
O) layer, the boron ion density closest to the wafer's surface can be maintained, resulting in low resistivity source/drain regions and high driving current, furthermore, semiconductor device performance is improved.
In one embodiment, a method for preventing boron segregation and out diffusion is provided. First of all, a semiconductor substrate is provided and forms a gate oxide layer as well as a gate layer on top of the semiconductor substrate. Next, a photoresist layer is formed on a top surface of the gate layer, moreover, pattern transfers onto the photoresist layer after going through an exposure and a development. Furthermore, the gate layer and the gate oxide layer are then etched by using the photoresist layer as a mask, and the photoresist layer is removed afterward. In succession, a thin nitride oxide (NO,N
2
O) layer is grown by utilizing rapid thermal oxidation (RTO) and rapid thermal nitridation (RTN) processes.
High doped drain regions (HDDs) of boron ion shallow junctions are then formed by carrying out ion implantation. A TEOS layer and a silicon nitride layer are deposited by using low pressure chemical vapor deposition (LPCVD), and spacers are formed by etching the silicon nitride layer and the TEOS layer. Next, a heavy doping of boron ions occurs as well as an annealing process. The final stage would be a procedure of forming metal silicides.


REFERENCES:
patent: 5221632 (1993-06-01), Kurimoto et al.
patent: 5744395 (1998-04-01), Shue et al.
patent: 5904517 (1999-05-01), Gardner et al.
patent: 5989966 (1999-11-01), Huang
patent: 6022785 (2000-02-01), Yeh et al.

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