Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-07-21
2002-10-01
Eckert, II, George C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S317000, C257S321000, C438S257000
Reexamination Certificate
active
06459121
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a non-volatile semiconductor memory device and, more particularly, to a non-volatile semiconductor memory device which has a self-aligned floating gate electrode formed by using a trench isolation structure and a method for producing the same.
FIGS. 16A
to
18
I show steps for producing a conventional non-volatile semiconductor memory device. As shown in
FIG. 16A
, linear trench isolations
2
are formed on a surface of a silicon semiconductor substrate by using a conventional technology. Then, the surface of the semiconductor substrate
1
is oxidized, thereby a tunnel film
3
made from silicon oxide is formed on the substrate
1
. A polycrystalline silicon layer is deposited and a floating gate electrode
4
is formed from the polycrystalline layer using a lithography technology. The floating gate
4
extends linearly and parallel to the trench isolations
2
. Then, n type ions are implanted into the substrate
1
, thereby n
−
diffusion layers
5
are formed parallel to the trench isolations
2
.
Then, as shown in
FIG. 16B
, an insulating film made from silicon oxide is deposited over the top surface of the semiconductor substrate
1
. The insulating film is then partially etched and remained on side walls of the floating gate electrodes
4
and, thereby, side spacers
6
are formed. Then, n
+
diffusion layers
7
are formed parallel to the trench isolations
2
by an ion implantation technology.
Then, as shown in
FIG. 16C
, thick insulating layer
8
′ having a thickness of about 5000-8000 Å is formed over the top surface of the semiconductor substrate
1
.
Also, as shown in
FIG. 17D
, the thick insulating layer is polished so that the top of the floating gate electrode
4
is exposed by CMP method, thereby flat insulating layers
8
are formed.
Further, as shown in
FIG. 17E
, a polycrystalline silicon layer is deposited over the surface of the semiconductor substrate
1
, and the polycrystalline silicon layer is etched to form fin-type floating gate electrodes
9
. The fin-type floating gate electrodes
9
extend linearly and parallel to the floating gate electrodes
4
.
Furthermore, as shown in
FIG. 17F
, an inter poly insulating film
10
is formed on the fin-type floating gate electrodes
9
and flat insulating layers
8
. For example, the inter poly insulating film
10
is made from a multi-layer film (an ONO film) of silicon oxide, silicon nitride and silicon oxide films or a multi-layer film (an ONON film) of silicon oxide, silicon nitride, silicon oxide and silicon nitride films.
Then, a two-layer film
11
of conducting and insulating layers is deposited on the inter poly insulating film
10
. Subsequently, as shown in
FIG. 18G
, illustrating a cross sectional view of a region with a word line, the two-layer film used for a control electrode
11
is remained. On the other hand, as shown in
FIG. 18H
, indicating a cross sectional view of a region without such a word line, the two-layer film is removed.
Further, as shown in
FIG. 18I
, the inter poly insulating films
10
, the fin-type floating gate electrodes
9
and the floating gate electrodes
4
are removed in the region without the word line.
Then, a non-volatile semiconductor memory device shown in
FIGS. 19A
to
19
C is completed. Note that
FIG. 19A
is a plan view of the non-volatile semiconductor memory device. Also,
FIG. 19B
is a cross sectional view of the region with a word line (along lines A—A), and
FIG. 19C
is a cross sectional view of the region without a word line (along lines B—B).
The non-volatile semiconductor memory shown in
FIGS. 19A
to
19
C comprises n
−
diffusion layers
5
and n
+
diffusion layers
7
extending parallel to the trench isolations
2
, and forming source/drain regions of memory cells. Hereinafter, the source and drain regions are referred to as a source and the drain lines, respectively. These lines are called as bit lines of a memory device. While the control electrode
11
is formed perpendicular to the trench isolation
2
, and the line is called as a word line of a memory device.
An equivalent circuit diagram of the non-volatile semiconductor memory is shown in FIG.
20
. In the diagram, the circuit comprises n pieces of memory cell, and memory cells
1
to n−1 are in write mode, and memory cell n is in erase mode. When reading information stored in the memory cell n, the drain line is biased to about 1V, the source line to 0V, the semiconductor substrate to 0V, the word lines
1
to n−1 to 0V and the word line n to about 5 V as shown in FIG.
20
.
However, the floating gate electrodes
4
may be formed out of the center of the two neighboring trench isolations
2
, after these isolations
2
has been formed at the alignment step for the trench isolations
2
. Therefore, the floating gate electrode
4
can often be shifted from the center of the isolations
2
.
In
FIG. 19B
, when the floating gate electrode
4
is shifted from the center to the right, widths of the n
−
diffusion layer
5
and n
+
diffusion layer
7
formed at the right side of the floating gate electrode
4
are smaller than those of the n
−
diffusion layer
5
and n
+
diffusion layer
7
formed at the left side of the electrode
4
. This results in that the resistance of the right drain line is higher than that of the left source line.
When the resistance of the drain line is higher than that of the source line, a voltage drop is occurred in the drain line. This presents the drain part of the memory cell n from being biased to 1V, although the drain line is biased to 1V. This in turn that the current flowing through the memory cell n becomes lower than Iread flowing in memory cell n at erase mode, therefore the memory cell n is erroneously detected to be in write mode.
Also, when misalignment of the floating gate electrode
4
against the center of the trench isolations
2
increases the resistance of the source or drain. Therefore, the length between the neighboring trench isolations
2
should be three times or more of the minimum resolution (F) using in lithography process. This results in that the unit memory cell
20
is 2 F long by 4 F wide and 8 F
2
in area in minimum.
Further, as shown in
FIG. 18I
, an etching residue
12
in the shadow portion of the side spacer
6
after the removal of the floating gate electrode
4
in the portion where no word line is formed may connect electrically between the floating gate electrodes
4
of the neighboring memory cells.
SUMMARY OF THE INVENTION
Accordingly, the first object of the present invention is to provide a non-volatile semiconductor memory device which detects information in write/erase mode of the memory cell with a certain precision by forming a floating gate electrode at the center of the neighboring trench isolations.
Also, the second object of the present invention is to provide a highly integrated non-volatile semiconductor memory device which comprises a memory cell smaller than 8 F
2
in area.
Also, the third object of the present invention is to provide a non-volatile semiconductor memory device which prevents a short-circuit between memory cells by removing etching residues on a side wall of a side spacer.
The present invention provides a method for producing a non-volatile semiconductor memory device. The method includes the steps of providing a semiconductor substrate having a surface, forming trench isolations on the substrate, the trench isolations being projected from the surface, forming source and drain regions between the neighboring trench isolations, so that the source and drain regions are faced each other across a channel region, and forming a floating gate electrode on the channel region through a tunnel film which is formed on the channel region.
By forming the floating gate electrode after forming the source/drain regions, the floating gate electrode can be formed at the center of the neighboring trench isolations, so that the width of the source region is substantially
Sakamoto Osamu
Shimizu Satoshi
Tsuji Naoki
Eckert II George C.
Mitsubishi Denki & Kabushiki Kaisha
LandOfFree
Method for producing non-violatile semiconductor memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for producing non-violatile semiconductor memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for producing non-violatile semiconductor memory... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2993902