Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2006-03-14
2006-03-14
Norton, Nadine G. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S714000, C438S715000, C438S719000, C257S254000, C257S417000
Reexamination Certificate
active
07012026
ABSTRACT:
A method of producing well-defined polycrystalline silicon regions is described, in particular for producing electrically conducting regions, in which a substrate is provided with an insulating layer and a layer of doped amorphous silicon, electromagnetic irradiation is performed using a laser source to produce the electrically conducting regions, and a shadow mask is positioned between the laser source and the substrate having the layer for definition of the contours of the electrically conducting regions.
REFERENCES:
patent: 4622856 (1986-11-01), Binder et al.
patent: 5518951 (1996-05-01), Paynter et al.
patent: 6140668 (2000-10-01), Mei et al.
patent: 6713330 (2004-03-01), Zhang et al.
Patent Abstracts of Japan vol. 005, No. 167 (E-079), Oct. 24, 1981 & JP 56 094622 A (Toshiba Corp), Jul. 31, 1981.
Patent Abstracts of Japan vol. 005, No. 023 (E-045), Feb. 12, 1981 & JP 55 150239 A (Mitsubishi Electric Corp), Nov. 22, 1980.
Emili Walter
Goebel Herbert
Wanka Harald
Kenyon & Kenyon
Norton Nadine G.
Tran Binh X.
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