Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-08-29
2004-05-11
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000, C438S637000, C438S759000
Reexamination Certificate
active
06734095
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for producing cavities (air gaps), which are patterned in submicrometer dimensions, in an cavity layer of a semiconductor device using a freezing process liquid, and to a configuration which is fabricated by the method and has cavities, which have been patterned in submicrometer dimensions, in a semiconductor device.
Within a semiconductor device, interconnects are capacitively coupled to one another both within an interconnect layer (intralevel) and between different interconnect layers (interlevel). Capacitive coupling between interconnects of this nature leads to crosstalk and lengthened signal propagation times.
To minimize the disruptive effects, the interconnects are decoupled from one another as best they can be by keeping the capacitance between them at as low a level as possible. For a given spacing between two interconnects, this requires the material between the interconnects to have the lowest possible permittivity. Gaseous substances, i.e. air, have a virtually optimal permittivity of almost 1 at standard pressure, while the permittivity of solids is generally much higher.
Therefore, it is generally attempted in semiconductor devices to capacitively decouple the interconnects from one another by use of air-filled cavities. The text that follows will describe the known methods for producing cavities of this type. All the methods are based on a process layer that has already been patterned by ribs and trenches.
In functional terms, the ribs of the process layer may be interconnects. The trenches in the process layer are as yet uncovered cavities. Accordingly, an interconnect layer is one possible (but not the only) embodiment of a cavity layer which results from the process layer.
According to a first method, the trenches are filled with porous materials, such as xerogels or aerogels, and are then covered with a covering layer made from a dielectric. The air which is enclosed in the pores reduces the overall permittivity of the material between the interconnects. Porous materials of this type are currently in the evaluation phase. Drawbacks of the method are the water uptake on account of the capillary effect in open-pored structures, and the relatively long process times. Furthermore, filling the cavities with xerogel and aerogel material increases the permittivity of the air gaps compared to a pure air filling. The use of aerogels as dielectrics with a low permittivity is described, for example, in the reference titled “The Effect Of Sol Viscosity On The Sol-Gel Derived Low-Density SiO
2
Xerogel Film For Intermetal Dielectric Application”, Thin Solid Films, vol. 332, p. 449-454, 1998.
A second method is for trenches to be covered by conventional SiO
2
chemical vapor deposition (CVD) processes with a high deposition rate.
A first variant of a method of this type is described in the reference by B. P. Shieh, et al., titled “Air-Gap Formation During IMD Deposition to Lower Interconnect Capacitance”, IEEE Electron Device Letters, Vol. 19, No. 1, pp. 16-18, January 1998. However, cavities produced in this way extend into the covering SiO
2
layer (formation of small hats). During subsequent chemical mechanical polishing (CMP) processes, the cavities below can be opened up, and adjacent interconnects can be short-circuited by subsequent metallization in the opened cavities. If the SiO
2
layer is deposited in a size that is such that it rules out subsequent opening of the cavities, the problem is then of making contact with interconnects below it through sufficiently deep vias.
In a variant of this method, described in the reference by T. Ueda, et al., titled “A Novel Air Gap Integration Scheme for Multi-level Interconnects using Self Aligned Via Plugs”, Symp. on VLSI Technology, pp. 46, 47, June 1998, the trenches are covered using a two-stage process. In a first stage, SiO
2
is deposited on the horizontal surfaces of the ribs using a plasma enhanced chemical vapor deposition (PECVD) process. Narrow trenches are covered by the SiO
2
that grows on the surfaces of the ribs on both sides of the trenches. In a subsequent high-density plasma CVD process, wider trenches are filled with SiO
2
and narrow trenches are sealed with SiO
2
.
According to a third method, described in the reference by J. G. Fleming, E. Roherty-Osmum, titled “Use of Air-Gap Structures to Lower Intralevel Capacitace”, Proc. DUMIC, pp. 139-145, 1997, spin-on materials are used to cover the cavities between the interconnects. The drawback of the method is the subsequent flow of the materials into the cavities.
A fourth method is described in International Patent Disclosure WO 97/39484 A1 (Rosenmayer, Noddin). In this method, a film is placed onto the interconnect layer, which has been patterned by trenches and ribs. A film of this type is at least a few micrometers thick, so that it can be reliably processed. Therefore, as above, there are considerable distances between the interconnect levels, with the drawbacks described of making contact using vias.
A fifth method, which is described in U.S. Pat. No. 6,165,890 (Kohl et al.), is the retropolymerization of polynorbornene, which temporarily fills the cavities between the interconnects. In this method, inevitable residues of the retropolymerization may lead to clusters that are critical with regard to short circuits. Furthermore, the choice of a dielectric between the interconnect layers is limited, since the material has to be permeable to the volatile substances which form during the retropolymerization.
Similar drawbacks result from a sixth method, the thermal decomposition of a temporary filling of the cavities between the interconnects. An example of thermal decomposition of a temporary filling with a photoresist is described in U.S. Pat. No. 5,668,398 (Havemann et al.). The oxidation of a temporary carbon layer forms the subject of a reference by M. B. Anand, M. Yamada, H. Shibata, titled “NURA: A Feasible, Gas Dielectric Interconnect Process”, Symp. on VLSI Technology, pp. 82, 83, June 1996. In both cases, the substances formed during the decomposition have to be forced through the covering layer, which restricts the choice of materials. The residues in the cavities that cannot be decomposed increase the permittivity and/or reduce the protection against short circuits. According to a further example, which is known from International Patent Disclosure WO 00/51177 (Werner, Pellerin), for the decomposition of a temporary filling, the covering layer is perforated before the decomposition of the filling, in order to accelerate or improve the expulsion of the decomposition residues.
According to a seventh method, which is known from U.S. Pat. No. 5,599,745 (Reinberg), a dielectric is applied to the ribs formed by the interconnects, is partially melted until this layer bulges out over the interconnect. The bulges in the covering layer of closely adjacent interconnects ultimately come into contact with one another, so that the trenches between them are spanned.
A description which summarizes known methods for producing cavities in a semiconductor substrate is described, together with an assessment of the results which can be achieved by these methods, in the article by Ben Shieh, Krishna Saraswat, Mike Deal, Jim McVittie, titled “Cavities Lower k Of Interconnect Dielectrics” Solid State Technology, February 1999.
To summarize, the drawbacks of the methods which have been described are:
a) residues in the cavities, which increase the permittivity and/or reduce the protection against short circuits;
b) the thickness required of the layer which covers the trenches, and the difficulty of producing vias which such a thickness implies; and
c) process integration.
Furthermore, freezing sublimation techniques are known from the fabrication of open trench structures in semiconductor components that have microstructures. In these techniques, after a purging operation semiconductor devices are dried by the purge liquid that is still on the semiconductor device initially being
Leuschner Rainer
Mergenthaler Egon
Estrada Michelle
Fourson George
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
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