Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – On insulating substrate or layer
Patent
1998-12-23
2000-11-21
Thomas, Tom
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
On insulating substrate or layer
438142, 438149, 438151, 438197, 438265, 438299, 438301, 438303, 438479, 438517, 438595, 438597, 438635, 438637, 438639, 257330, 257332, 257347, 257377, 257382, 257383, 257384, 257389, 257395, 257408, 257412, H01L 2120, H01L 2130, H01L 21301, H01L 2134
Patent
active
061502413
DESCRIPTION:
BRIEF SUMMARY
DESCRIPTION
1. Background of the Invention
This invention relates to a field effect transistor in which the field insulation and contact areas are self-aligned with its active region, and a process for making this transistor.
More precisely, the invention relates to the manufacture of this transistor on a Silicon On Insulator type substrate, subsequently referred to as SOI in the rest of the text.
Applications of the invention include microelectronics for the manufacture of Metal Oxide Semiconductor (MOS) type devices, and particularly for integrated circuits useable in an environment subject to radiation.
2. Discussion of the Background
The state of the art closest to the invention is shown in FIG. 1 in the appendix. This figure diagramatically shows a cross-section through the structure of a MOS type transistor 10 made on an SOI substrate. The active region 12 of the transistor 10 is formed in a silicon thin film 14 covering a buried layer of silicon oxide SiO.sub.2 16.
The active region 12 is delimited by thick silicon oxide pads 17 of the LOCOS (LOCalized Oxidation of Silicon) type formed in the silicon thin film 14. The pads 17 mutually isolate the different transistors made on the same SOI substrate. A grid structure 18 comprises a stack, with a grid insulator layer 20, a grid 22, and a shunt layer 24 forming a contact area on grid 20 and lateral spacers 26 formed on the stack flanks, in order.
The grid structure 18 is placed above the transistor channel 28 and the source region 30 and drain region 32 are formed by doping the thin film 14 on each side of the grid structure.
A thick layer 34 of BPSG (borophosphosilicate glass) type glass covers the active region 12 and surrounds the grid structure 18.
Contact holes 36, 38 formed in the glass layer 34, vertically in line with the source 30 and drain 32, and metal 40 formed in holes 36, 38 form conductive tracks connecting the source and drain to metallic interconnection lines 42, 44 respectively formed on layer 34.
A large number of photolithography steps are necessary to define its components and to make a transistor according to FIG. 1.
A first step is necessary to form the field oxide pads 17. A second photolithography step is used to make the grid structure 18. Finally, a photolithography step is necessary to make the contact holes in the glass layer 34.
Formation of the grid structure 18 comprises deposition of the grid insulator layer 20, the grid layer 22 and the shunt layer 24, then etching these layers using a mask defining the shape and dimensions of the grid structure. The position of the mask defining the grid with respect to the mask used to define the oxide pads is difficult for devices with high integration. Thus, the process is incapable of making a very precise alignment of the grid on the active area, and carrier type inversion problems are observed on the flanks of the active area. These problems are due particularly to coupling between the grid and the flanks of the active area when the field insulation is partially removed in the field area.
Another difficulty in making the transistor in FIG. 1 is due to the alignment of contact holes on the source and drain regions. This difficulty also forms a limitation to miniaturization of devices.
SUMMARY OF THE INVENTION
Thus, one purpose of the invention is to propose a transistor and its manufacturing process on an SOI substrate which does not have any of the difficulties mentioned above.
Another purpose is particularly to propose a process in which firstly the grid is automatically aligned with the active region comprising the channel, and secondly the contact areas are automatically aligned with the grid. Another purpose of the invention is to propose a process with a minimum number of photolithography steps.
Another purpose of the invention is to propose a transistor enabling total control with low inversion. The low inversion condition is the condition in which the transistor is conducting under the conducting limit at high inversion conditions. It is considered that total control
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Hwang J M et als: "Ultra-Trin Film SOI/CMOS With Selective-EPI Source/Drain for Low Series Resistance, High Drive Current" Symposium on VLSI Technology. Digest of Technical Papers, Honolulu, Jun. 7-9, 1994 No. Symp.14, Jun. 7 1994, Institute of Electrical and Electronics Engineers, p. 33/34 XP000498570.
Commissariat a l''Energie Atomique
Souw Bernard E.
Thomas Tom
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