Method for producing a thin semiconductor chip comprising an...

Details Method for producing a thin semiconductor chip comprising an... Method for producing a thin semiconductor chip comprising an...

2011-05-31

2011-05-31

Smith, Matthew S (Department: 2823)

Semiconductor device manufacturing: process

Semiconductor substrate dicing

Having specified scribe region structure

C438S705000, C257SE21287, C257SE21570

Reexamination Certificate

active

07951691

ABSTRACT:
In a method for producing a thin film chip including an integrated circuit, a semi-conductor wafer having a first surface is provided. At least one cavity is produced under a defined section of the first surface by means of porous silicon. A circuit structure is produced in the defined section. The defined wafer section is subsequently released from the semiconductor wafer by severing local web-like connections, which hold the wafer section above the cavity and on the remaining semiconductor wafer.

REFERENCES:
patent: 6165813 (2000-12-01), Quinn et al.
patent: 6285072 (2001-09-01), Maeda
patent: 6342433 (2002-01-01), Ohmi et al.
patent: 6521068 (2003-02-01), Menschig et al.
patent: 6566235 (2003-05-01), Nishida et al.
patent: 6774010 (2004-08-01), Chu et al.
patent: 6825057 (2004-11-01), Heyers et al.
patent: 6972215 (2005-12-01), Sakaguchi et al.
patent: 2001/0014516 (2001-08-01), Shimoji
patent: 2002/0146893 (2002-10-01), Shimoda et al.
patent: 2002/0153595 (2002-10-01), Tayanaka
patent: 2005/0029224 (2005-02-01), Aspar et al.
patent: 2005/0104223 (2005-05-01), Huang et al.
patent: 40 29 973 (1992-03-01), None
patent: 197 52 208 (1999-06-01), None
patent: 100 19 705 (2001-05-01), None
patent: 2 823 596 (2002-10-01), None
patent: 2002-299500 (2002-10-01), None
patent: 2005/104223 (2005-11-01), None
Imai et al, “Crystalline Quality of Silicon Layer Formed by FIPOS Technology”, 1983, Journal of Crystal Growth 63(1983), 547-553.
T. Overstolz et al.; “A Clean Wafer-Scale Chip-Release Process Without Dicing Based on Vapor Phase Etching”; Jan. 2004; pp. 717-720.
Takao Yonehara et al.; “ELTRAN® Novel SOI Wafer Technology”; Jul. 2001; pp. 10-16.
Camille Darnaud-Dufour et al.; “Canon ELTRAN What's SOI”; Feb. 2006; 3 pages.
S. Armbruster et al.; “Surface Micromachining of Monocrystalline Silicon Membranes Using a Silicon Micro Grid on Sintered Porous Silicon”; Sep. 2004; pp. 22-23.
C. Berge et al.; “150-mm layer transfer for monocrystalline silicon solar cells”; 2006; pp. 3102-3107.

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