Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2004-10-18
2009-11-03
Gebremariam, Samuel A (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S153000, C438S154000, C438S164000, C438S406000, C438S469000, C438S761000, C438S762000, C438S763000, C438S479000
Reexamination Certificate
active
07611928
ABSTRACT:
Substrate having a first partial substrate with a carrier layer and a second partial substrate, which is bonded to the first partial substrate. The second partial substrate has an insulator layer, which is applied on the carrier layer and has at least two regions each having a different thickness, thereby forming a stepped surface of the insulator layer, and a semiconductor layer, which is applied to the stepped surface of the insulator layer and is formed at least partially epitaxially, wherein the semiconductor layer has a planar surface which is opposite to the stepped surface of the insulator layer. Transistors are formed on the semiconductor layer.
REFERENCES:
patent: 4399605 (1983-08-01), Dash et al.
patent: 5070034 (1991-12-01), Satoh et al.
patent: 5234535 (1993-08-01), Beyer et al.
patent: 5279978 (1994-01-01), See et al.
patent: 5534459 (1996-07-01), Kim
patent: 6329689 (2001-12-01), Manning
patent: 6492209 (2002-12-01), Krishnan et al.
patent: 6514809 (2003-02-01), Xiang
patent: 6712288 (2004-03-01), Yanagita et al.
patent: 0 810 652 (1997-12-01), None
patent: 3-211876 (1991-09-01), None
patent: 4-323851 (1991-11-01), None
patent: 6-104412 (1994-04-01), None
patent: 6-163677 (1994-06-01), None
patent: 6-252016 (1994-09-01), None
patent: 2000-306993 (2000-11-01), None
patent: 2000-349267 (2000-12-01), None
patent: 2001-102442 (2001-04-01), None
patent: 2001-320033 (2001-11-01), None
patent: 2002-026137 (2002-01-01), None
patent: 2002-075917 (2002-03-01), None
B. Eitan et al.; “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell”; IEEE Electron Device Letters, vol. 21, No. 11, Nov. 2000, pp. 543-545.
H. Hanafi et al.; “Fast and Long Retention-Time Nano-Crystal Memory”; IEEE Transactions on Electron Devices, vol. 43, No. 9, Sep. 1996, pp. 1553-1558.
D. Widmann et al.; “Technologie hochintegrierter Schaltungen” (Technology of Largescale Integrated Circuits), Chapter 8.4, Springer Verlag, Berlin, ISBN 3-540-59357-8(1996).
Homepage Firma Soitec (Feb. 12, 2002): http://www.soitec.com/unibont.htm.
Hofmann Franz
Luyken Richard Johannes
Roesner Wolfgang
Specht Michael
Stadele Martin
Dickstein , Shapiro, LLP.
Gebremariam Samuel A
Infineon - Technologies AG
LandOfFree
Method for producing a substrate does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for producing a substrate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for producing a substrate will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4105202