Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2002-09-30
2004-10-26
Le, Dung A. (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S596000, C438S597000, C216S069000, C216S070000
Reexamination Certificate
active
06809019
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a method for producing a semiconductor structure, and to use of the method.
Manufacturers of semiconductor components, in particular, manufacturers of integrated circuits, are always interested in developing and using new methods for producing semiconductor structures for reasons related to cost, reasons associated with simplification of the manufacturing methods, reasons associated with progressive miniaturization of semiconductor structures, or reasons related to intellectual property.
Prior art methods are disclosed, for example, in European Patent Application 0 901 157 A2, in U.S. Pat. No. 5,885,900 to Schwartz and in U.S. Pat. No. 5,335,138 to Sandhu et al. Furthermore, the subject matter of German Published, Non-Prosecuted Patent Application 100 22 656.6, corresponding to U.S. Patent Publication 2002/019138 A1 to Gerhard et al., also deals with the production of semiconductor structures.
U.S. Pat. No. 6,037,206 to Huang et al. discloses a method for producing a capacitor for a dynamic random access memory, in which a first conductive layer is applied to an insulating layer, and a photoresist layer is applied to the first conductive layer. The latter leaves the first conductive layer partially exposed. The first conductive layer is etched to partially expose the insulating layer. In the process, fence-like plates are produced at the edges of the first conductive layer, and on the residues of the photoresist. The latter is then removed. A further conductive layer is then applied, which merges with the first conductive layer, with the fence-like plates and with the exposed surfaces of the insulating layer. In the process, sharp edges are created on the fence-like plates and on the further conductive layer, which are then rounded by etching.
U.S. Pat. No. 5,792,593 to McClure et al. discloses the etching of an initial material, in which this material rests on the side walls of a vertically running surface of a further material.
U.S. Pat. No. 6,210,595 B1 to Weinrich et al. and U.S. Pat. No. 5,938,250 to Onken also have similar disclosure contents.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for producing a semiconductor structure, and use of the method that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that provides a further, modern method for producing a semiconductor structure, as well as one possible use of this method.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a method for producing a semiconductor structure, including the steps of applying a first layer to a substrate, applying a masking layer to the first layer, etching the first layer utilizing the masking layer as a mask to produce fences, removing the masking layer, applying an auxiliary layer to mechanically stabilize the fences, and subsequently removing the auxiliary layer and the fences except for a predetermined thickness of the auxiliary layer measured from a surface of the substrate.
In accordance with another mode of the invention, the etching step is carried out with an ion milling method.
In accordance with a further mode of the invention, at least one second layer is applied to the first layer before applying the masking layer, and the etching step is carried out by at least etching the second layer in addition to the first layer.
In accordance with an added mode of the invention, the auxiliary layer and the fences are removed by chemical-mechanical polishing.
In accordance with an additional mode of the invention, before application of the first layer, the substrate is treated to produce a local projection at the substrate.
In accordance with yet another mode of the invention, the first layer application step is carried out by applying a first layer to a substrate having a local projection.
In accordance with yet a further mode of the invention, a local projection is produced at the substrate before application of the first layer.
With the objects of the invention in view, there is also provided a method for producing a semiconductor structure, including the steps of applying a first layer to a surface of a substrate, applying a masking layer to the first layer, producing fences by etching the first layer and masking the first layer with the masking layer, removing the masking layer, mechanically stabilizing the fences by applying an auxiliary layer, and subsequently removing the auxiliary layer and the fences except for a predetermined thickness of the auxiliary layer measured from the substrate surface.
With the objects of the invention in view, there is also provided a method for producing spacers in a semiconductor structure, including the steps of applying a first layer to a substrate, applying a masking layer to the first layer, etching the first layer utilizing the masking layer as a mask to produce fences, removing the masking layer, applying an auxiliary layer to mechanically stabilize the fences, and producing spacers at the substrate by subsequently removing the auxiliary layer and the fences except for a predetermined thickness of the auxiliary layer measured from a surface of the substrate.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for producing a semiconductor structure, and use of the method, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 5335138 (1994-08-01), Sandhu et al.
patent: 5792593 (1998-08-01), McClure et al.
patent: 5885900 (1999-03-01), Schwartz
patent: 5998250 (1999-12-01), Andricacos et al.
patent: 6037206 (2000-03-01), Huang et al.
patent: 6210595 (2001-04-01), Weinrich et al.
patent: 2002/0019138 (2002-02-01), Beitel et al.
patent: 100 22 656 (2001-11-01), None
patent: 0 901 157 (1999-03-01), None
Hartner Walter
Krönke Matthias
Greenberg Laurence A.
Infineon - Technologies AG
Le Dung A.
Locher Ralph E.
Stemer Werner A.
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