Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-07-07
2001-11-20
Abraham, Fetsum (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S348000, C257S349000, C257S350000, C257S059000, C257S072000
Reexamination Certificate
active
06320224
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for effectively forming a contact hole and a capacitor in a semiconductor integrated circuit.
2. Description of the Related Art
In a semiconductor integrated circuit, a multilayer wiring structure is used, it is necessary to form a contact hole for connecting with wirings one another and an element such as a capacitor (condenser). To obtain the multilayer wiring structure, an interlayer insulator is formed in general, so that insulation and capacitance between the wirings are decreased. In a portion required to connect with the wirings one another, a contact hole is formed in the interlayer insulator. When a capacitor is formed, the interlayer insulator itself may be used as dielectric. However, since the interlayer insulator is used to decrease insulation and capacitance between the wirings, when the interlayer insulator is used as dielectric of the capacitor, an area of the capacitor is extremely large and thus loss is great in a circuit design.
If an interlayer insulator is thin, the capacitor having a large capacitance can be formed in the same area. However, to achieve this, it is necessary to remove the interlayer insulator completely in a contact hole forming portion and to etch the interlayer insulator suitably (until a suitable thickness required to form a capacitor) in a capacitor forming portion. Thus, it is impossible to use such the capacitor actually in mass production process.
To operate a capacitor effectively, it is required that a thickness of a portion of an interlayer insulator used as dielectric is ⅕ to {fraction (1/50)} thinner than an initial thickness of an interlayer insulator. If a capacitance of a capacitor is 100 times larger than that of an intersection portion of a normal wiring and an interlayer insulator formed in a portion of the capacitor has the same thickness as the intersection portion of the normal wiring, it is required that an area of the capacitor is 1000 times larger than that of the intersection portion of the wiring. On the other hand, if a thickness of the portion of the capacitor is {fraction (1/10)}, the area of the capacitor is 100 times larger than that of the intersection portion, and thus it is effective in integration of elements. However, for example, it is impossible to etch an interlayer insulator by 90% in thickness to and remain it by only 10% in thickness. Thus, precision control cannot be performed substantially in a desired area.
SUMMARY OF THE INVENTION
In the present invention, an interlayer insulator is constructed by at least two materials (such as an upper layer and a lower layer) each having different dry etching characteristics. When the upper layer is etched by dry etching, a thickness of the lower layer can be controlled precisely by using the lower layer as an etching stopper. By using a first mask, a desired region in the upper layer can be etched selectively.
After the desired region in the upper layer is etched and removed, the lower layer is etched selectively using a second mask in a contact hole forming portion. This etching process may be dry etching or wet etching. In a capacitor forming portion, the lower layer is covered with a mask to prevent etching. In an etching condition for the lower layer, when the upper layer is not etched sufficiently, the second mask may be used to expose a portion other than the portion etched by using the first mask.
In particular, in the present invention, when the Interlayer insulator has two layer structures wherein the upper layer is formed by a material containing mainly silicon nitride and the lower layer is formed by a material containing mainly silicon oxide, it is superior because dry etching characteristics are different largely each other.
A transparent conductive material such as ITO (indium tin oxide) may be used as the second mask. For example, a pixel electrode in a TFT array of an active matrix type liquid crystal display can be used as the second mask. In this case, a photolithography process can be omitted.
According to the present invention, there is provided a method for producing an semiconductor integrated circuit comprising the steps of: forming an interlayer insulator including at least upper and lower layers each having different dry etching characteristics; etching the upper layer of the interlayer insulator using a first mask, wherein the lower layer of the interlayer insulator is used as an etching stopper; forming a second mask to cover a portion of the lower layer of the interlayer insulator exposed by the etching step; selectively etching the lower layer of the interlayer insulator using the second mask; forming a contact hole in one portion that the upper and lower layers of the interlayer insulator are etched; and forming a capacitor in another portion that only the upper layer of the interlayer insulator is etched.
According to the present invention, there is provided a method for producing an semiconductor integrated circuit comprising the steps of: forming an interlayer insulator including upper and lower layers, wherein the upper layer has silicon nitride and the lower layer has silicon oxide; etching the upper layer of the interlayer insulator using a first mask, wherein the lower layer of the interlayer insulator is used as an etching stopper; forming a second mask to cover a portion of the lower layer of the interlayer insulator exposed by the etching step; selectively etching the lower layer of the interlayer insulator using the second mask; forming a contact hole in one portion that the upper and lower layers of the interlayer insulator are etched; and forming a capacitor in another portion that only the upper layer of the interlayer insulator is etched.
According to the present invention, a thickness of dielectric of a capacitor is determined by a thickness of a lower layer of an interlayer insulator. In an upper layer etching process, since the lower layer serves as an etching stopper, the thickness of dielectric of a capacitor can be uniform in an entire area. When a thickness of the lower layer of the interlayer insulator is ⅕ to {fraction (1/50)} of an entire thickness of the interlayer insulator, since a thickness of dielectric of the capacitor can be sufficiently thin, it is effective to reduce an area of the capacitor. When a dielectric constant of a material used in the upper layer is different from that of a material used in the lower layer, it is necessary to consider its effect.
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Abraham Fetsum
Nixon & Peabody LLP
Robinson Eric J.
Semiconductor Energy Laboratory Co,. Ltd.
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