Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2000-08-31
2002-04-30
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S305000
Reexamination Certificate
active
06380053
ABSTRACT:
BACKGROUND OF THE INVENTION AND RELATED ART STATEMENT
The present invention relates to a method for producing a semiconductor device, particularly to a method for producing a semiconductor device in which an impurity concentration profile of an extension region positioned between a channel forming region and each source/drain region can be controlled accurately.
With increasing shrinkage of semiconductor devices, the integration degree is doubled every three years according to a scaling rule, and speed of semiconductor devices is increasing and power consumption thereof is decreasing. The production of finer MOS type FETs has been being accomplished by decreasing a dimension of a gate electrode, decreasing a thickness of a gate insulating layer and highly accurately controlling an impurity concentration profile in a channel forming region or in its vicinity. And, driving capability of semiconductor devices is improved and a parasitic capacitance thereof is decreased according to finer semiconductor devices. In general, in circuits having a CMOS structure, an operating rate is determined depending upon a rate of charging (or discharging) for giving an output of a logic gate at a certain stage to drive a capacitive load in a subsequent logic gate. Therefore, the operating rate is in proportion to the inverse number of capacity of the capacitive load and to the driving capability.
For accomplishing the formation of finer semiconductor devices, conventionally, there has been employed an LDD (lightly doped drain) structure for forming a source/drain region, i.e., a structure having a low-concentration-impurity-containing region which is formed between each source/drain region and a channel forming region and extends from each source/drain region. In this structure, an electric field near a drain region can be reduced and the change of the semiconductor device caused by hot carriers with elapse of time (an increase in threshold voltage Vth and a decrease in driving capability) can be suppressed. In semiconductor devices finely structured in recent years, however, not only it is required to decrease a supply voltage, but also it is rather required to highly accurately control an impurity concentration profile in an impurity-containing region formed between each source/drain region and a channel forming region than it is required to attain reliability with regard to the hot carriers. For decreasing a parasitic capacitance of the impurity-containing region formed between each source/drain region and the channel-forming region, the impurity-containing region is arranged to have relatively high impurity concentration in many cases in recent years. The impurity-containing region formed between each source/drain region and the channel-forming region will be referred to as “extension region” hereinafter in the present specification. The impurity concentration in the extension region is lower than the impurity concentration in the source/drain region in some cases, equal to the same in some cases, and higher than the same in some cases. That is, the impurity concentration in the extension region is determined depending upon the characteristic required of semiconductor devices.
The method of forming a conventional extension region will be explained with reference to schematic partial cross-sectional views of a semiconductor substrate, etc., shown in
FIGS. 9A
,
9
B and
10
hereinafter.
[Step-10]
A device isolation region
11
having a LOCOS structure is formed, for example, in a semiconductor substrate
10
by a known method, followed by well ion-implanting, channel stop ion-implanting and threshold value adjusting ion-implanting. The device isolation region
11
may have a trench structure, or it may be a combination of a LOCOS structure and a trench structure. Then, the surface of the semiconductor substrate
10
is thermally oxidized to form a gate insulating layer
20
. Then, a polysilicon layer
21
A and a tungsten silicide layer
21
B are formed on the entire surface, and the tungsten silicide layer
21
B and the polysilicon layer
21
A are patterned by a lighography method and a dry etching method, whereby a gate electrode
21
having a polycide structure can be formed on the gate insulating layer
20
.
[Step-20]
For forming an extension region
125
, then, the exposed silicon semiconductor substrate
10
is ion-implanted (see FIG.
9
A). Then, a first heat treatment for activation is carried out for activating the impurity brought by the ion-implantation and recovering the semiconductor substrate
10
from a crystal defect caused by the ion-implantation. When the above first heat treatment for activation is omitted, the impurity brought by the ion-implantation may be abnormally diffused (enhanced diffusion) at a process temperature around 700° C. applied during formation of a thin layer, for example, by a chemical vapor deposition method (CVD method) in a subsequent step, due to the crystal defect caused in the silicon semiconductor substrate
10
by the ion-implantation, and the impurity concentration profile may vary to a great extent. In the above manner, the extension region
125
can be formed.
[Step-30]
Then an insulating material layer composed, for example, of SiO
2
is deposited on the entire surface by a CVD method, and the insulating material layer is etched back, to form gate-side-walls
122
on the side walls of the gate electrode
21
(see FIG.
9
B).
[Step-40]
[Step-40]
For forming source/drain regions, then, the exposed silicon semiconductor substrate
10
is ion-implanted (see FIG.
10
), and a second heat treatment for activation is carried out for activating the impurity brought by the ion-implantation, whereby source/drain regions
23
and a channel-forming region
24
interposed between the source/drain regions
23
can be formed. The channel-forming region
24
is located immediately below the gate electrode
21
. Each extension region
125
is positioned between each source/drain region
23
and the channel-forming region
24
and extends from each source/drain region
23
.
In the method of forming the above conventional extension region, the thermal budget (effective heat treatment quantity) in the extension region is always higher than the thermal budget in the source/drain region for the following reason. The sourcejdrain region is subjected to the heat treatment for activation once, but the extension region is subjected to the heat treatment for activation twice.
For improving the impurity concentration profile in the extension region to make it higher than the impurity concentration profile in the source/drain region, it is required to decrease the impurity concentration in the extension region. When the impurity concentration in the extension region is decreased, however, there is caused the following problem. The resistance of the extension region increases, a parasitic resistance in the semiconductor device increases, and as a result, the driving capability decreases. The parasitic resistance in the extension region and the control of the impurity concentration profile in the extension region have a trade-off relationship, which comes to represent a great difficulty. Further, if the impurity concentration in the extension region is not increased, the driving capability decreases due to an increase in the parasitic resistance. If the impurity concentration is increased to excess, it is difficult to produce a finer-structured semiconductor device with suppressing a short channel effect.
The broadening of the impurity concentration profile in the extension region in a lateral direction particularly increases an overlap capacitance between the marginal portion of the gate electrode and the source/drain region and decreases the operating rate of the semiconductor device to a great extent.
Under the circumstances, the optimization of the impurity concentration and the accurate controlling of the impurity concentration profile in the extension region are increasingly acquiring importance in the production of
Elms Richard
Owens Beth E.
Sonnenschein Nath & Rosenthal
Sony Corporation
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