Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate
Reexamination Certificate
2003-07-17
2004-09-14
Lee, Calvin (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having schottky gate
C438S254000, C438S397000, C257S309000, C257S332000
Reexamination Certificate
active
06790717
ABSTRACT:
DESCRIPTION
The invention relates to a method for fabricating a semiconductor component having a metallic contact electrode that is T-shaped in cross section, in particular a field-effect transistor with a T-shaped metal gate.
In field-effect transistors, the gate length is a dimension that critically determines the limiting frequency of the transistor, so that the shortest possible gate length is sought for high frequencies. On the other hand, the lead resistance of the gate electrode is also intended to be as low as possible. The features of short gate length and low lead resistance can be realized in particular by means of metallic gate electrodes with a narrow gate base and a wide gate head by comparison therewith, so-called T-shaped electrodes (T gate).
Very small gate lengths in the submicron range, in particular less than 0.2 &mgr;m, can currently be fabricated only with limited reliability using direct optical lithography.
DE 39 11 512 A1 discloses a self-aligning method for fabricating a control electrode in which openings for structures of source and drain electrodes are produced photolithographically in a resist layer. By means of undercutting, the region between the source and drain structures is intended to be reduced to a narrow dummy gate which, in a later method stage, surrounded by a new resist layer, centers the etching of a gate head structure and is removed before the deposition of the gate metal. However, in reality the undercutting leads to a dummy gate form having a widened base. The undercutting is not reproducible with sufficient precision. In addition, the distance between the openings for the structures of source and drain electrodes cannot be set sufficiently accurately as an initial basis for the width of the dummy gate during the direct optical lithography.
The technique of defining a lateral structure in the submicron range by means of a layer, deposited on a vertical step sidewall, as auxiliary layer having a thickness that can be set accurately has long been known per se. By way of example, IEEE Electron Device Letters, EDL-2, No 1, January 1981, pp. 4-6 by Hunter et al., A New Edge-Defined Approach for Submicrometer MOSFET Fabrication, describes a method in which two elements with lateral submicron dimensions produced with respect to the sidewalls of a step structure serve, after the removal of the step structure, as masks for producing very narrow gate structures in underlying layers. Such elements produced on vertical sidewalls are also referred to as side spacers or hereinafter also simply as spacers.
DE 195 48 058 C2 describes a method for fabricating a MOS transistor in which spacers are produced on spaced-apart sidewalls of a structure produced photolithographically, which spacers serve as a mask for a subsequent etching of an underlying conductive first electrode layer, so that material webs remain as gate base below the spacers. A second electrode layer deposited thereabove over the whole area is patterned photolithographically in order to produce a gate head.
In EP 0 240 683, the gate length of a GaAs JFET is defined by an SiN spacer on a vertical edge of a photoresist structure. After a planarization of the SiN spacer, the latter masks the etching of the highly doped cap layer and thus defines the gate of the JFET.
A corresponding procedure is disclosed in U.S. Pat. No. 5,202,272 for fabricating a FET using silicon technology.
JP 04-196 135 A shows a method for fabricating a T gate with a short gate ength by producing an SiO
2
spacer on a vertical edge of a photoresist mask deposited above a semiconductor substrate, which spacer serves as a dummy for the gate base in a ate base layer and is removed again. In a head layer deposited thereabove, an opening as structure for the gate head is produced using a separate mask. In a uniform deposition step, the gate metal for forming the T-shaped gate is deposited into the gap of the dummy gate and the opening in the head layer. In an intermediate step, the spacer on the vertical edge of the photoresist mask may also serve for the self-aligning production of a low-impedance source region.
In a method disclosed in JP 02-208 945, a spacer is likewise produced on a vertical edge a a dummy gate and is subsequently removed with additional etching of a recess trench before a further photoresist layer is deposited and, in the latter, an opening for the structure of the gate head is produced above the gap of the dummy gate by means of a separate mask. Gate metal for forming a T-shaped gate is deposited into the opening of the further photoresist layer and into the gap of the dummy gate and excess metal on the further photoresist layer is removed by lift-off.
U.S. Pat. No. 5,391,510 describes a method in which a dummy gate is produced by means of a spacer on a vertical layer edge, which dummy gate is surrounded by an insulator layer and is removed to leave a gap which forms the structure for the gate base. The T-shaped gate is completed by whole-area deposition of a gate metal layer and subsequent etching.
EP 0 177 129 discloses a method in which the gate is defined directly by a metallic spacer, but without the possibility of producing a wider gate head.
EP 0 591 608 A2 describes a first fabrication method, which combines optical lithography for the gate head and electron beam lithography for the gate base by means of two different photoresist layers deposited one above the other. However, electron beam lithography is an expensive and time-consuming step in production with an unsatisfactory yield.
Therefore, the same document proposes a new method, in which an insulator layer is deposited onto the semiconductor material and a vertical step is produced in said insulator layer by means of optical lithography. A metal layer deposited over the area is also deposited on the vertical step sidewall. After planarization and production of a gate head mask above the vertical step, it is possible to remove the metal layer on the step sidewall. The resulting gap serves as a mask for the etching of a recess trench and for the deposition of the gate base metal. The layer thickness of the metal layer deposited on the step sidewall can be set very accurately according to known methods, so that a very short gate length can be realized in a reliable manner. However, the risk of misalignment between gate base and gate head arises as a result of the separate lithography steps for the vertical step, on the one hand, and the gate head mask.
The known method comprises further disadvantageous steps, in particular, in the advanced stage of fabrication, etching processes with an open recess trench and/or partly uncovered semiconductor contact layers, which can adversely affect the properties of the component.
In a method disclosed in U.S. Pat. No. 5,399,896, firstly a recess trench is defined with a first spacer (outside spacer) on a step sidewall and by means of an Al implantation and, on the resulting sidewalls of the recess trench, further spacer layers (inside spacer) are produced in a manner facing one another, whose lateral spacing determines the gate length and is filled with gate metal. The gate length actually produced depends on the lateral dimensions of the first and of the further spacers, which are in turn influenced by the heights of the respective vertical steps. Poor reproducibility of the gate length is expected due to the multiplicity of parameters influencing the gate length. What is disadvantageous about the method, moreover, is that the recess bottom can be damaged during the second spacer etching, which can lead to an impairment of the component properties.
The invention is based on the object of specifying an advantageous method for fabricating a T-shaped electrode with a very narrow electrode base.
The invention is described in patent claim
1
. The dependent claims contain advantageous refinements and developments of the invention. The invention is described below on the basis of the preferred use for the fabrication of a gate electrode of a field-effect transistor as electrode of a semiconductor com
Collard & Roe P.C.
United Monolithic Semiconductors GmbH
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