Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Patent
1998-07-06
2000-02-29
Monin, Jr., Donald L.
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
438127, 438613, H01L 2348
Patent
active
060308540
ABSTRACT:
An apparatus and method for forming solder interconnection structures that reduce thermo-mechanical stresses at the solder joints of a semiconductor device and its supporting substrate. In one embodiment, the solder interconnection structure of the present invention comprises a semiconductor device and a substrate having a plurality of solder connections extending from the substrate to electrodes or bond pads on the semiconductor device. A multilayer structure is disposed between the semiconductor device and substrate filling the gap formed by the solder connections. The multilayer structure includes a first layer and a second layer, each having a different coefficient of thermal expansion. Thus, in accordance with the present invention, the stress concentration points are moved away from the solder joints of the semiconductor device and substrate to a point located between the first and second layers of the filler structure.
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Inoue Shuji
Kubota Jiro
Kuroda Mashahiro
Mashimoto Yohko
Dietrich Mike
Intel Corporation
Monin, Jr. Donald L.
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