Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1997-05-08
2000-11-14
Niebling, John F.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438273, 438373, 438527, 438657, 438719, H01L 21336, H01L 21331, H01L 213205
Patent
active
061469823
ABSTRACT:
A method for producing a low-impedance contact between a metallizing layer and a semiconductor material of a first conductivity type having a semiconductor surface, an insulation layer on the semiconductor surface and a semiconductor layer on the insulation layer, includes applying a first insulating layer with a predetermined content of dopants on the semiconductor layer, and structuring the first insulating layer by anisotropic etching, forming first and second openings. The semiconductor layer is anisotropically etched by using the first insulating layer as a mask. A first dopant of a second conductivity type is implanted and driven through the first opening into the semiconductor material with a first phototechnique, forming a first zone in the semiconductor material. A second dopant of the first conductivity type is implanted through the second opening into the semiconductor material with a second phototechnique. A second doped insulating layer is applied over the entire surface. The second insulating layer is anisotropically back-etched down to the semiconductor surface, with peripheral insulating webs remaining in the first opening. The semiconductor material is self-adjustingly anisotropically etched down to the first zone, by using the second insulating layer as a mask. A third dopant of higher doping and of the second conductivity type is implanted into the first zone by using the second insulating layer as a mask. A metallizing layer is applied.
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Preussger Andreas
Werner Wolfgang
Wiesinger Klaus
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Nguyen Ha Tran
Niebling John F.
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