Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Having heterojunction
Reexamination Certificate
1999-07-30
2002-04-02
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Having heterojunction
C438S318000, C438S359000
Reexamination Certificate
active
06365477
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims the priority of German Application No. 198 34 491.0, filed in Jul. 31, 1998, the disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
The invention relates to a method for producing a heterobipolar transistor that is formed on a substrate of semiconductor material by initially growing a sequence of semiconductor layers for an emitter, a base and a collector, and a heterobipolar transistor produced according to the method.
Components with outstanding high-frequency characteristics are required for producing high-frequency circuits, e.g. power amplifiers, oscillators or mixers. An increase in the limiting frequencies f
T
and f
max
of transistors in this case represents an important precondition for technical innovation in the field of mobile or short-range communication systems, as well as phase-array antennas.
To date, transistors are known from the reference by Shigematsu, H. et al.; IEEE Electron Device Letters, Vol. 16, No. 2, pp. 55-57, (1995), which discloses a method for producing an InP/InGaAs heterobipolar transistor in connection with a polyimide planarizing technique for the base contacting, for use with high frequencies. The component production takes place by means of a self-adjustment processing sequence on an involved, so-called dummy emitter structure with spacers. The desirable goal therefore would be to find the simplest possible production method, for which the processing sequence is reliable and which allows a lowering of parasitic capacities.
It follows from the references by Asbeck, P. M. et al.; IEEE Electron Device Letters, Vo. EDL-5, No. 8, pp. 310-312, (1984) and Ho, M. C. et al.; IEEE Electron Device Letters, Vol. 16; No. 11, pp.512-514, (1995), for example, that other methods use the implantation process for insulating the extrinsic region of the base. The implantation process always causes damage to this base region, which results in an undesirable increase in the base-collector-capacity and thus a worsening of the high-frequency characteristics of a transistor.
It is the object of the invention to provide a method which makes it possible to optimize the high-frequency characteristics of a heterobipolar transistor by minimizing the parasitic base collector capacity, so as to effect an increase in the limiting frequencies f
T
and f
max
, as well as a transistor formed according to the method.
SUMMARY OF THE INVENTION
The above object generally is achieved according to the present invention by a method for producing a heterobipolar transistor, arranged on a substrate of semiconductor material which comprises: growing a semiconductor layer sequence for a collector, a base and an emitter on the surface of the substrate; configuring the transistor in a mesa design with the outer surface of the base layer being covered by a protective layer of at least one adjacent emitter layer; carrying out a first planarizing step by forming an insulating layer on the upper surface of the substrate to the outer limit of the base layers; partially removing a portion the at least one adjacent emitter layer to expose the upper surface of the base layer; forming a base contact on the exposed surface of the base layer; carrying out a second planarizing step by forming a second insulating layer on the upper surface of the substrate to at least the outer surface of the emitter layer; and, forming surface contacts for the emitter, base and collector by forming openings in the insulating layer where necessary and then depositing a final coating of metal. A method according to claim
1
, wherein polyimide layers are used on the insulating layer during the first and second planarizing steps. Advantageous embodiments and modifications of the invention likewise are disclosed and discussed.
The invention includes a two-stage method for planarizing a semiconductor surface with polyimide. In contrast to the state of the technology, this method prevents potential damage to the extrinsic region of the base. The processing sequence involves the growth of a layer sequence on a substrate of semiconductor material, on which layers for a collector, a base and an emitter are deposited one above the other. The transistor is subsequently configured in a mesa design. Following this, a first planarizing step up to the base mesa is realized, wherein during this first planarizing step, a remaining portion of the following emitter layer protects the surface of the base. This protective layer is subsequently removed, e.g., through a wet chemical etching that causes little damage, and the metal layer is deposited on the base. The base mesa has extremely small dimensions, so that the base metal expands laterally over the first planarizing layer and, in particular, a metal conducting strip is guided across the planarizing layer for the contacting. In a second planarizing step, a level semiconductor surface is generated up to and over the emitter mesa.
One particular advantage of the invention is that the high-frequency characteristics of a transistor can be optimized through minimizing the parasitic base collector capacity C
BC
by protecting on the one hand the base layers during the processing and by providing the base with correspondingly narrow dimensions. Another advantage of the planarizing results from the fact that technologically the individual steps of the processing sequence can be controlled easily, wherein the material selection, for example, is not limited to InP, but can also be extended to other semiconductor layer sequences. The invention is explained below with the aid of advantageous embodiments and by referring to the schematic drawings in the Figures.
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Gässler Christoph
Leier Helmut
Shin Hyunchol
Daimler-Chrysler AG
Kunitz Norman N.
Nguyen Tuan H.
Venable
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