Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2008-04-22
2008-04-22
Toledo, Fernando L (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C257S065000, C423S349000
Reexamination Certificate
active
07361592
ABSTRACT:
The method successively comprises production, on a substrate, of a stack of layers comprising at least one first layer made from germanium and silicon compound initially having a germanium concentration comprised between 10% and 50%. The first layer is arranged between second layers having germanium concentrations comprised between 0% and 10%. Then a first zone corresponding to the germanium-based element and having at least a first lateral dimension comprised between 10 nm and 500 nm is delineated by etching in said stack. Then at least lateral thermal oxidization of the first zone is performed so that a silica layer forms on the surface of the first zone and that, in the first layer, a central zone of condensed germanium forms, constituting the germanium-based element.
REFERENCES:
patent: 5917981 (1999-06-01), Kovacic et al.
patent: 6423632 (2002-07-01), Samavedam et al.
patent: 7205210 (2007-04-01), Barr et al.
patent: 2004/0115900 (2004-06-01), Huang et al.
patent: 2004/0219767 (2004-11-01), Arena et al.
patent: 2005/0156268 (2005-07-01), Chu
patent: 2005/0181549 (2005-08-01), Barr et al.
patent: 2005/0218453 (2005-10-01), Langdo et al.
patent: 2005/0224875 (2005-10-01), Anderson et al.
patent: 2007/0023756 (2007-02-01), Anderson et al.
patent: 2 852 144 (2004-09-01), None
patent: WO 2004/001810 (2003-12-01), None
Tezuka et al., “High-Mobility Strained SiGe-on-Insulator pMOSFETs With Ge-Rich Surface Channels Fabricated by Local Condensation Technique,” IEEE Electron Device Letters, vol. 26, No. 4, Apr. 2005, pp. 243-245.
Nakaharai et al., “Characterization of 7-nm-thick strained Ge-on-insulator layer fabricated by Ge-condensation technique,” Applied Physics Letters, vol. 83, No. 17, Oct. 2003, pp. 3516-3518.
Morand Yves
Poiroux Thierry
Vinet Maud
Commissariat a l''Energie Atomique
Oliff & Berridg,e PLC
ST Microelectronics SA
Toledo Fernando L
LandOfFree
Method for producing a component comprising at least one... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for producing a component comprising at least one..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for producing a component comprising at least one... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2783835