Method for producing a circuit board and a circuit-board preform

Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device

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Details

430312, 430313, 430318, 430319, 427 96, 174250, G03C 500

Patent

active

051399245

DESCRIPTION:

BRIEF SUMMARY
The present invention relates to a method for producing a circuit board on which electronic components and electrical circuits are to be mounted and connected together, wherein mutually electrically isolated and intersection electrical conductors are placed in a substrate layer, suitably to form an X/Y matrix, and the substrate layer together with the conductors encapsulated therein is treated in a manner to establish interruptions in the various conductor paths at specific locations therealong and to establish permanent electrical contact between mutually intersection conductor paths at given points of intersection. The invention also relates to a circuit-board preform for carrying out the method in the production of such circuit boards.
Conventionally, the conductor pattern or lay-out on a circuit board is produced with the combined aid of photographic and printing techniques. This process is both time consuming and expensive, however, especially when producing prototype boards or boards in small series. The problems encountered in the manufacture of such circuit boards increase with the development of progressively smaller components and circuits which are required to be placed in very close proximity with one another on such circuit boards. In this case, it is normally necessary to configure the conductor lay-out in several layers in the board, which makes the board still more expensive and still more difficult to produce; among other things because it is normally necessary to drill connecting holes through the board layers and to plate the holes, in order to establish the requisite electrical connections between the various layers.
In order to simplify the procedure required to achieve desired conductor patterns or lay-outs, the manufacturers of such circuit boards have recently begun to use a technique which is smaller to the older so-called wiring technique, in which insulated conductors are drawn between and connected to desired points on a circuit board with the aid of a complicated machine; c.f. for instance U.S. Pat. No. 3,674,914. This technique requires the conductor to be glued to the circuit board and is also time consuming and costly.
The present invention is based on the realization that a circuit board which is to carry closely packed electrical conductors and circuits having desired conductor lay-outs could be produced in a much simpler and far less expensive manner, by using a single layer foil or thin plate having embodied therein a conductor arrangement, suitably an x/y matrix, of closely packed, insulated conductors. The desired conductor pattern can then be established by breaking the various conductor paths at given points of intersection. This assumes, however, that reliable connections can be established easily between the conductor lay-out encapsulated in the foil and suitable contact points for external electrical components and circuits, and that the aforesaid breaks or interruptions in the conductor paths can be effected rationally.
A technique of this general kind is described in Canadian Patent No. 919 819, this technique utilizing a catalytic substrate material. In this case, for the purpose of establishing contact with the conductors in the conductor pattern, or conductor lay-out, the conductors are first drilled and the wall of the resultant holes then plated.
The plating is intended to be in electrical contact with the cut surfaces of the conductors. Thus, this known method requires holes to be drilled individually at all intersection points, which represents a highly time-consuming procedure. Furthermore, electrical contact with the conductors is established solely at the points of connection with the cut conductor surfaces. This procedure cannot be relied upon to be effective when using very thin conductors and when the contact between the cut conductor surfaces and the plating is subjected to stresses engendered by temperature-induced movement between the conductive material and the substrate or base material. Because of the difficulty in achieving an acceptable elec

REFERENCES:
patent: 3525617 (1970-08-01), Bingham
patent: 4528261 (1985-07-01), Hauser
patent: 4642160 (1987-02-01), Burgess
patent: 4915983 (1990-04-01), Lake et al.

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