Electrical computers and digital processing systems: multicomput – Computer-to-computer protocol implementing – Computer-to-computer data transfer regulating
Patent
1997-05-13
1999-08-03
Dinh, Dung C.
Electrical computers and digital processing systems: multicomput
Computer-to-computer protocol implementing
Computer-to-computer data transfer regulating
709237, 709250, 712 18, 710 56, G06F 15163
Patent
active
059319151
ABSTRACT:
A message-passing protocol for accommodating early arrival messages passed between source and destination nodes in a computer system with a plurality of asynchronous computing nodes interconnected by bidirectional asynchronous communications channels. The protocol includes transmitting the message from sender to receiver without waiting for a request for the message from the receiver; determining at the receiver if a receive buffer has been posted for the message; and if the receive buffer has not been posted for the message, then either truncating the message by storing its message header in an early arrival queue at the receiver and discarding its data or allocating a temporary receive buffer at the receiver to hold the message data. Upon the receiver being ready to post a receive buffer for an early arrival message, the receiver checks the early arrival queue for the corresponding message header, and if the message header is in the early arrival queue and the message data has been discarded, then the receiver sends a pull request to the sender to retransmit the message to the receiver.
REFERENCES:
patent: 4494194 (1985-01-01), Harris et al.
patent: 4748617 (1988-05-01), Drewlo
patent: 5014187 (1991-05-01), Debize et al.
patent: 5047917 (1991-09-01), Athas et al.
patent: 5208914 (1993-05-01), Wilson et al.
patent: 5404562 (1995-04-01), Heller et al.
patent: 5444860 (1995-08-01), Datwyler et al.
patent: 5488723 (1996-01-01), Baradel et al.
patent: 5764641 (1998-06-01), Lin
"Two-Level DMA from Channels to Main Store", IBM Technical Disclosure Bulletin, vol. 32, No. 12, May 1990.
"Method for Handling Disabled Memory Blocks with Simulated Failures", IBM Technical Disclosure Bulletin, vol. 38, No. 09, Sep. 1995.
"Data Rate Matching Buffer", IBM Technical Disclosure Bulletin, vol. 29, No. 4, Sep. 1986.
"Asynchronous/Queued I/O Processor Architecture", IBM Technical Disclosure Bulletin, vol. 36, No. 1 Jan. 1993.
Benner Alan F.
Grassi Michael
Dinh Dung C.
International Business Machines - Corporation
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