Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
1999-12-13
2001-05-01
Powell, William (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C216S018000, C216S038000, C216S088000, C438S740000, C438S754000
Reexamination Certificate
active
06225226
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
This invention relates generally to fabrication of a semiconductor device and more particularly to a method for forming a copper structure, such as interconnections without performing a copper chemical-mechanical polishing (CMP) step, reducing the risk of copper contamination.
2. Description of the Prior Art
Integrated circuits continue to increase in complexity each year. As applications develop for memories, microprocessors, and minicomputers there is an increasing demand for greater microminiturization, greater switching speeds, and smaller and less costly integrated circuit semiconductor devices.
Increased device microminiturization improves device performance and packing density while reducing cost per unit. However, microminiturization reduces yield and reliability, and degrades interconnect performance and noise margins.
Continued microminiturization of semiconductor devices using non-scaling aluminum lines would require the use of more metal layers, multi-level interconnections, and global planarization. The use of copper for interconnect and line metallurgy has long been considered as a possible alternative metallization material to aluminum and aluminum alloys due to its low resistivity and ability to reliably carry high current densities. However, its use has presented many manufacturing problems, such as the possibility of diffusion into the semiconductor substrate, the low adhesive strength of copper to various dielectric materials, and the difficulty in planarizing a copper layer without erosion or dishing occuring which reduces the performance and impedes the ability to stack multiple layers.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,011,580 (Pan et al.) discloses a copper plating process where a photoresist layer is used as a mask to form copper lines/interconnects during a rework process. However, this patent does not disclose or suggest planarizing the copper structures.
U.S. Pat. No. 5,693,568 (Lui et al.) shows a process for a dual-damascene shaped interconnect by depositing metals and patterning.
U.S. Pat. No. 5,691,238 (Avanzino et al.) shows a subtractive dual-damascene process.
U.S. Pat. No. 5,674,787 (Zhao et al.) teaches a copper interconnect formed by a selective electroless copper deposition.
U.S. Pat. No. 5,429,987 (Allen) teaches a copper interconnect formed by a selective copper deposition.
U.S. Pat. No. 4,980,034 (Volfson et al.) describes, generally, subtractive processes to form metal lines/interconnects.
U.S. Pat. No. 5,891,804 (Havermann et al.) teches a selective copper interconnect method.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for forming a copper structure with reduced risk of copper contamination.
It is another object of the present invention to provide a method for forming a copper structure without using a copper CMP process.
It is another object of the present invention to provide a method for forming a copper structure which is compatible with multi-layer architecture.
It is yet another object of the present invention to provide a producible and economical method for forming copper interconnects and lines in tenches in a dielectic layer using a self-aligned copper electroplating process.
To accomplish the above objectives, the present invention provides a method for forming copper interconnects, without inducing copper diffusion, by eliminating the copper chemical-mechanical polishing process. A semiconductor structure is provided having a first metal layer thereover. A first inter-metal dielectric layer is formed over the first metal layer and planarized. A first resist layer is formed over the first inter-metal dielectric layer, and the first resist layer and the first inter-metal dielectric layer are patterned to form via openings with the first metal layer forming the bottoms of the via openings. A seed layer is formed on the sidewalls and bottoms of the via openings. A self-align layer, composed of a high-resistivity, inorganic material, is formed over the seed layer. The self-align layer is patterned to reform the via openings and to form trench openings, exposing the seed layer on the bottoms and sidewalls of the via openings and on the bottoms of the trench openings. A copper layer is electroplated onto the exposed seed layer at the bottoms and sidewalls of the via openings and on the bottom of the trenches. The remaining portions of the self-align layer removed, then the exposed portions of the seed layer are removed.
The present invention provides considerable improvement over the prior art. Because no copper chemical-mechanical polishing is required, the risk of copper migration and reduced dielectric strength and/or shorting is reduced. The method of the present invention can be economically performed using existing semiconductor processing equipment and technology.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.
REFERENCES:
patent: 4980034 (1990-12-01), Volfson et al.
patent: 5011580 (1991-04-01), Pan et al.
patent: 5429987 (1995-07-01), Allen
patent: 5674787 (1997-10-01), Zhao et al.
patent: 5691238 (1997-11-01), Avanzino et al.
patent: 5693568 (1997-12-01), Liu et al.
patent: 5891804 (1999-04-01), Havemann et al.
patent: 6121146 (2000-09-01), Yoon et al.
patent: 6127258 (2000-10-01), Watanabe et al.
patent: 6150272 (2000-11-01), Liu et al.
Chen Chien-Chen
Lee Fu-Sheng
Lin Chen-Ting
Lu Cheh-Chieh
Ackerman Stephen B.
Powell William
Saile George O.
Stoffel William J.
Taiwan Semiconductor Manufacturing Company
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