Method for processing an interlevel dielectric suitable for VLSI

Details Method for processing an interlevel dielectric suitable for VLSI Method for processing an interlevel dielectric suitable for VLSI

1986-02-24

1988-06-28

Bueker, Richard R.

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Making electrical device

430314, 430317, 430330, G03C 500

Patent

active

047538660

ABSTRACT:
A method of processing an interlevel dielectric layer in a VLSI device having a plurality of leads which includes depositing a layer of photoresist over the dielectric layer. The photoresist is then patterned to open areas where interlevel contacts are to be formed and then heated to a sufficiently high temperature and for a sufficient time to remove solvents and obtain a desired slope surrounding the open areas. The photoresist and dielectric is etched to planarize the dielectric surface, to expose the underlying leads and to remove all of the photoresist.

REFERENCES:
patent: 4508815 (1985-04-01), Ackmann et al.
patent: 4549927 (1985-10-01), Goth et al.
patent: 4605470 (1987-08-01), Gwozdz et al.
IBM Tech. Discl. Bulletin, vol. 27, No. 2, Jul., 1984, Doublecoat Planar Polyimide Process, J. P. Kent, pp. 1149-1150.
A. C. Adams, "Plasma Planarization", Solid State Technology, 178, Apr. 1981.

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