Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-09-13
2003-03-04
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180, C365S185290
Reexamination Certificate
active
06529413
ABSTRACT:
This application relies for priority on Korean Patent Application No. 2000-63184, filed on Oct. 26, 2000, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to nonvolatile storage devices, and, in particular, to a flash memory device with an improved program algorithm capable of reducing program time.
BACKGROUND OF THE INVENTION
Generally, semiconductor memory devices for storing data are classified into volatile semiconductor memory devices and nonvolatile semiconductor memory devices. The volatile semiconductor memory devices lose their data at power-off, and the nonvolatile semiconductor memory devices maintain their data even at power-off. Therefore, the nonvolatile semiconductor memory devices have been widely used at applications in which power can be unexpectedly interrupted.
The nonvolatile semiconductor memory devices comprise electrically erasable and programmable ROM cells which are referred to as “flash EEPROM cells” or “flash memory cells.”
FIG. 1
shows a cross-sectional view of the flash memory cell. The flash memory cell, as illustrated in
FIG. 1
, has a semiconductor substrate (or bulk)
1
of a first conductive type (e.g., P type), source and drain regions
2
and
3
of a second conductive type (e.g., N type) spaced apart relative to each other, a floating gate
6
storing charges and placed over a channel region between the source and drain regions
2
and
3
, with a thin insulation film
4
having a thickness of about 100 Å interposed therebetween, and a control gate
8
placed over the floating gate
6
, with another insulation film
7
interposed therebetween. The control gate
8
is connected to a word line.
The table below shows typical source, drain, control gate and bulk voltages according to program, read, erase and erase repair operations of a flash memory cell.
TABLE
Read
Program
Erase
Erase repair
Vg
14.5 V
10 V
−10 V
~2 V
Vd
1 V
5 V~6 V
Floating
5 V~6 V
Vs
0 V
0 V
Floating
0 V
Vb
0 V
0 V
5 V~10 V
0 V
The program operation of the flash memory cell is performed by biasing a substrate
1
and a source region
2
with a ground voltage and the drain region
3
with a positive voltage (e.g., 5 V~6 V) appropriate to generate hot electrons. According to this program operation, a sufficient amount of charges are stored in the floating gate
6
, thus the floating gate
8
has a negative voltage. This means that a threshold voltage of the programmed flash memory cell is increased when performing the read operation.
During the read operation where a positive voltage (e.g., 4.5 V) is applied to the control gate
8
and the ground voltage is applied to the source region
3
, no channel of the programmed memory cell is formed. That is, current from the drain region
3
to the source region through the channel is cut off. At this time, the memory cell has an “off” state, and a threshold voltage thereof is distributed in a range of 6 V to 7 V, as illustrated in FIG.
2
.
Flash memory cells in a sector are simultaneously erased by a F-N (Flower-Nordheim) tunneling mechanism. According to the F-N tunneling mechanism, a negative high voltage (e.g., −10 V) is applied to the control gate
9
and a positive voltage (e.g., 5 V to 10 V) is applied to the semiconductor substrate
1
. At this time, as seen from the table, the source and drain regions
2
and
3
are maintained at a floating state of high-impedance. An erase operation of this bias condition is named a “Negative Gate and Bulk Erase (NGBE)” operation. By such a bias condition, an electric field of about 6~7 millivolts (mV)/cm is formed across the tunneling oxide film
4
or between the control gate
8
and the semiconductor substrate
1
, and negative charges accumulated in the floating gate
6
are emitted via the tunneling oxide layer
4
to the semiconductor substrate
2
via a mechanism such as the F-N tunneling. This causes the effective threshold voltage of the cell to be reduced to within a range of about 1 V to 3 V. As its effective threshold voltage is reduced, the cell transistor enters a conductive state (i.e., an “on” state) when a read voltage is applied to the control gate
8
during the read operation.
Various erase methods associated with the flash memory device are disclosed in U.S. Pat. No. 5,781,477 entitled “FLASH MEMORY SYSTEM HAVING FAST ERASE OPERATION”, U.S. Pat. No. 5,132,935 entitled “ERASURE OF EEPROM MEMORY ARRAYS TO PREVENT OVER-ERASED CELLS”, U.S. Pat. No. 5,220,533 entitled “METHOD AND APPARATUS FOR PREVENTING OVERERASURE IN A FLASH CELL”, U.S. Pat. No. 5,513,193 entitled “NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE CAPABLE OF CHECKING THE THRESHOLD VALUE OF MEMORY CELLS”, and U.S. Pat. No. 5,805,501 entitled “FLASH MEMORY DEVICE WITH MULTIPLE CHECKPOINT ERASE SUSPEND LOGIC”.
The erase verify operation determines whether all memory cells in a sector after the NGBE operation exist in a target threshold voltage range (e.g., 1 V~3 V) corresponding to the on state. The erase verify operation is performed by biasing the control gate with an erase verify voltage of about 3 V and the drain region with a voltage of about 5 V. At this time, the source region and the semiconductor substrate are grounded.
Commonly, a threshold voltage of the erased flash memory cell is distributed in a range of 1 V to 3 V. Nevertheless when all memory cells of the sector are simultaneously erased, a threshold voltage of a flash memory cell may be lowered below 1 V. Such a flash memory cell is named “an over-erased memory cell”. The over-erased memory cell(s) can be repaired by an erase repair operation (referred to as a post program operation or an over-erase repair operation), in which the threshold voltage of the over-erased cell is shifted in a target threshold voltage range (e.g., 1 V~3 V) corresponding to the on state.
The erase repair operation is performed by biasing the source region and the semiconductor substrate of the over-erased memory cell with the ground voltage and the control gate thereof with a voltage of about 3 V. Under this bias condition, negative charges less than that of the program operation are accumulated in the floating gate. Thus, by performing the erase repair operation, the threshold voltage of the over-erased flash memory cell can be shifted in the target threshold voltage range of the on state as illustrated in FIG.
2
.
In general, memory cells of the sector are erased according to a set of algorithms including a pre-program algorithm, a main erase algorithm and a post-program algorithm. The pre-program algorithm corresponds to the above-mentioned program process, and the post-program algorithm corresponds to the above-mentioned erase repair process. The main erase algorithm corresponds to the above-mentioned erase process. A flowchart illustrating a main erase algorithm according to the prior art is illustrated in FIG.
3
.
In order to perform a sector (or block) erase operation, first, an address counter, an erase loop counter and a bulk step counter are initialized (S
10
). The address counter generates an address for appointing memory cells to be selected by the byte or word, the erase loop counter is used to limit loop times consisting of a set of NGBE and erase verify operations, and the bulk step counter is used to step a bulk voltage. After initializing, the NGBE and erase verify operations are performed in a subsequent step S
20
. The NGBE operation to a selected sector is performed during a predetermined period of time (e.g., 2~5 seconds) according to the above-mentioned bias condition.
After the NGBE operation, the erase verify operation is carried out which is to judge whether the threshold voltages of the erased memory cells are distributed below an upper limit value (e.g., 3 V) of a threshold voltage distribution corresponding to the on or erased state. Such an erase verify operation is identical to a read operation with the exceptio
Lee June
Lim Young-Ho
Auduong Gene N.
Hoang Huan
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
LandOfFree
Method for preventing over-erasing of memory cells and flash... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for preventing over-erasing of memory cells and flash..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for preventing over-erasing of memory cells and flash... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3027440