Method for preventing micromasking in shallow trench isolation p

Details Method for preventing micromasking in shallow trench isolation p Method for preventing micromasking in shallow trench isolation p

1997-12-30

2000-06-27

Utech, Benjamin L.

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

438706, 438711, 438712, 438724, H01L 2176

Patent

active

06080677&

ABSTRACT:
An isolation structure on an integrated circuit is formed using a shallow trench isolation process. A layer of buffer oxide is formed on a substrate. A layer of nitride is formed on the layer of buffer oxide. The layer of nitride and the layer of buffer oxide are patterned to form a trench area. The substrate including the trench area is subjected to a plasma comprising H.sub.2 O vapor, and a gaseous fluorocarbon or a fluorinated hydrocarbon gas to clean impurities on the trench area. The substrate is etched to form a trench within the trench area.

REFERENCES:
patent: 5436190 (1995-07-01), Yang et al.
patent: 5445710 (1995-08-01), Hori et al.
patent: 5693147 (1997-12-01), Ward et al.
patent: 5719085 (1998-02-01), Moon et al.
patent: 5879575 (1999-03-01), Tepman et al.

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