Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
1999-06-04
2001-06-05
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S473000, C438S680000, C438S758000
Reexamination Certificate
active
06242365
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related to a method for preventing a target film deposited on a wafer in production from cracking, and more particularly to a method for preventing an undoped silicon glass (USG) film deposited on a wafer in production by a chemical vapor deposition process from cracking after a post annealing procedure.
BACKGROUND OF THE INVENTION
An undoped silicon glass (USG) film deposited by a chemical vapor deposition (CVD) process has been widely used in the field of IC fabrication as a shallow trench isolation (STI) gap fill, sidewall spacer, inter-metal dielectric (IMD) or passivation dielectric. For the CVD process, O
3
/TEOS is preferred over SiH
4
due to better gap fill or step coverage capability as well as safety consideration. On the other hand, a sub atmosphere (SA) CVD process is prior to an atmosphere (AP) CVD process and a plasma enhanced (PE) CVD process to serve as the deposition technique for depositing the USG film because of the better balance in the deposition rate and the gap fill capability. Therefore, so far, an SA O
3
/TEOS process is commonly used for the deposition of a USG film.
The SA O
3
/TEOS process, however, still suffers from a drawback that the as-deposited film is porous and inclined to absorb moisture. Therefore, a post annealing procedure will be necessary to densify the film. In the meantime, the within film tensile stress is subject to elevation during the thermal annealing procedure so as to cause the film crack. Therefore, the situation of the USG film during the IC production is generally checked to detect or even prevent the crack of the film, and it is preferred to adopt a non-destructive method.
Several parameters of the within film such as the deposition rate and the HF etching rate have been monitored to determine the crack limit of the film in order to prevent from cracking, but none of them is sensitive enough to serve as an indicator to achieve this purpose. In addition, a painstaking scanning electron microscope (SEM) process can be used to check the situation of the USG film via an off line operation, and the SEM results generally tell the crack situation of the film rather than prevent it.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a method for determining a crack limit of a target film deposited on a wafer in production without any destruction.
Another object of the present invention is to prevent a target film deposited on a wafer in production from cracking after a post annealing procedure by previously determining a crack limit.
According to the present invention, a method for preventing a target film deposited on a wafer in production from cracking after a post annealing procedure includes steps of:
a) forming a plurality of target films on respective bare wafers;
b) annealing the bare wafers with the target films;
c) observing whether the target films on the bare wafers crack;
d) detecting thermal shrinkage rates of the target films on the bare wafers to determine a crack limit when there is film cracking observed in the step c);
e) adjusting deposition conditions and repeating the steps a) and b), and then detecting thermal shrinkage rates of the target films newly formed on bare wafers;
f) repeating the step e) until no target films on bare wafers having thermal shrinkage rates exceeding the crack limit; and
g) allowing the target film to be deposited on the wafer in production under the adjusted deposition conditions.
Preferably, the plurality of target films are formed on the respective bare wafers with at least two kinds of thickness in order to make the test results on the bare wafers as complete as possible. More preferably, at least one of the at least two kinds of thickness approximates to the thickness of the target film to be deposited on the wafer in production. For obtaining comparable results, the conditions for forming and annealing the target films on the bare wafers are preferably identical to those for forming and annealing the target film on the wafer in production.
If there is film cracking on the bare wafers observed in the step c), then each of the thermal shrinkage rates (SR) of the target films which do no crack is defined by an equation of SR=(T
1
−T
2
)/T
1
, in which T
1
indicates the thickness of a target film detected before the annealing procedure, and T
2
indicates the thickness of a target film detected after the annealing procedure.
After the thermal shrinkage rates are determined, the crack limit can be determined for example by selecting the highest one of the thermal shrinkage rates of the annealed target films which do not crack as a threshold value, and subtracting a buffer value from the threshold value to have the crack limit. The presence of the buffer value is for further assuring of the perfection of the target film on the wafer in production when the test results on bare wafers are applied to the production wafers. As for the selection of the buffer value, it can be made by a trial and error method, or as large as possible provided that other desired properties are not influenced significantly.
In the step e), the deposition conditions to be adjusted include a flowing rate of a chemical precursor. Alternatively, the deposition conditions to be adjusted include a mechanical state of a deposition system for forming the target film on the wafer in production provided that the deposition system for forming the target film on the wafer in production is the same as that for forming the target films on the bare wafers.
The method according to the present invention, on the other hand, further includes a step after the step c) of directly depositing the USG film on the wafer in production under the same deposition conditions as the step a) if there is no film cracking observed in the step c).
The present method for example can be applied to a USG film formed by a SACVD process on a wafer with a MOS layer and a contact.
REFERENCES:
patent: 5989983 (1999-12-01), Goo et al.
Chu Jason C. S.
Hung Roger Tun-Fu
Lin Jerry C. S.
Wu Chih-Ta
Bowers Charles
Conlin David G.
Corless Peter F.
Edwards & Angell LLP
Kilday Lisa
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