Method for preventing crosstalk between conductive layers

Details Method for preventing crosstalk between conductive layers Method for preventing crosstalk between conductive layers

1998-12-17

2001-02-06

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S618000, C438S761000

Reexamination Certificate

active

06184122

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for preventing crosstalk between conductive layers on a semiconductor device. More particularly, the present invention relates to a method for preventing horizontal and vertical crosstalk between conductive layers using a dummy conductive layer on a semiconductor substrate.
2. Description of the Related Art
As the integration density of semiconductor devices increases, more circuit elements must to be packed in a unit surface area of the device substrate, and circuit elements such as interconnects are necessarily increased between MOS transistors of the IC device. In many highly integrated semiconductor devices, more than two levels of interconnecting metal layers are demanded, called multilevel interconnects. Between these multiple metal layers, electrically insulating material known as inter-metal dielectrics are used to provide isolation in between the metal layers. Vias are formed in these inter-metal dielectric layers that can be filled with electrically conductive material to form plugs that provide electrical connection between the interconnects for different metal layers.
As shown in
FIG. 1
, planar conductive lines
108
are isolated by an inter-metal dielectric layer
104
on a substrate
100
. Another conductive layer
110
is formed on the inter-metal dielectric layers
104
. An inter-metal dielectric layer
106
is formed on the conductive layer
110
. Another conductive layer
112
is formed on the inter-metal dielectric layer
106
. The inter-metal dielectric layers
104
and
106
are formed to isolate the conductive layers
108
,
110
and
112
and avoid any unwanted connection. In order to make interconnection between any of these conductive layers
108
,
110
and
112
, an interconnection structure is formed.
Multilevel interconnect structure includes conductive layers, conductive lines and plugs. The conductive lines are either located side by side and are isolated by inter-metal dielectric layer or else the conductive layers are located level by level and are connected by a plug. The planar conductive lines
108
and the conductive layer
110
are isolated by inter-metal dielectric layer
104
, and the conductive layers
110
and
112
for different levels are isolated by inter-metal dielectric layer
106
.
Semiconductor miniaturization results in reducing the distance between the interconnects. Electric fields are induced while charges flow through the interconnects. The distance between the conductive lines
108
is shorter than before, which induces electric field interference between the conductive lines
108
in a phenomenon known as horizontal crosstalk. Horizontal crosstalk can affect mobility of charges in the conductive lines
108
, which reduces device performance. Similarly, the distances between the conductive lines
108
and the conductive layer
110
are shortened, which induces electric field interference between the conductive lines
108
and conductive layer
110
in a phenomenon known as vertical crosstalk. Vertical crosstalk can also affect mobility of charges in the conductive lines
108
and conductive layer
110
, which reduces device performance.
Additionally, as the thickness of the inter-metal dielectric layers
104
between planar conductive lines
108
or between the conductive lines
108
and conductive layer
110
for different levels becomes thinner, an induced capacitance
114
becomes more obvious. The phenomenon is undesirable in the multilevel interconnects process.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method for preventing horizontal and vertical crosstalk between conductive layers on a semiconductor device.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for preventing horizontal and vertical crosstalk between conductive layers on a semiconductor device to avoid device failure. A dielectric layer is formed on a substrate, and a plurality of conductive lines are formed on the dielectric layer, then an over etching step is performed on the exposed dielectric layer to form a recess thereon to expose the dielectric layer underlying the conductive lines. An insulation layer is deposited conformal to the substrate, the level of the insulation layer on the recess bottom is lower than that of the interface of the conductive layers and the dielectric layer. A dummy conductive layer is deposited on the insulation layer, wherein a portion of dummy conductive layers isolates the conductive lines to prevent horizontal crosstalk between the conductive lines.
This invention provides another method for preventing horizontal and vertical crosstalk between conductive layers. A dielectric layer is formed on a substrate and a first metallic layer and a second metallic layer are both formed within the dielectric layer, which first and second metallic layers are located on different levels and are isolated from each other by the dielectric layer. A via is formed between the first and the second metallic layers to connect them to each other and an insulation layer is formed around the via. A dummy conductive layer is formed between the first and the second metallic layers. The first metallic layer and the dummy conductive layer are isolated by the dielectric layer, the second metallic layer and the dummy conductive layer are also isolated by the dielectric layer, and the via and the dummy conductive layer are isolated by the insulation layer. The present method prevents vertical crosstalk between the first and the second metallic layers.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 6060383 (2000-05-01), Nogami et al.

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