Method for preventing circuit failures due to gate oxide...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Reexamination Certificate

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07127689

ABSTRACT:
A method is disclosed for preventing circuit failures due to gate oxide leakage, and is used to efficiently check many nets of a circuit on a chip or within a macro to find logical fails due to gate oxide leakage using DC calculations, wherein the gate leakage is treated as a noise source for a static noise analysis of the circuit.

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patent: 2002/0027391 (2002-03-01), Hutamura et al.
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patent: 2005/0007153 (2005-01-01), Ding et al.
patent: 2005/0218934 (2005-10-01), Lee et al.
R, Rodriquez-Montanes, J.A. Segura, V.H. Champac, J. Figueras and J.A. Rubio, Current vs. logic testing of gate oxide short floating gate bridging failures in CMOS, Proc. Int. Test Conf., pp. 510-519, Oct. 1991.

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