Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-10-24
2006-10-24
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
07127689
ABSTRACT:
A method is disclosed for preventing circuit failures due to gate oxide leakage, and is used to efficiently check many nets of a circuit on a chip or within a macro to find logical fails due to gate oxide leakage using DC calculations, wherein the gate leakage is treated as a noise source for a static noise analysis of the circuit.
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R, Rodriquez-Montanes, J.A. Segura, V.H. Champac, J. Figueras and J.A. Rubio, Current vs. logic testing of gate oxide short floating gate bridging failures in CMOS, Proc. Int. Test Conf., pp. 510-519, Oct. 1991.
Kartschoke Paul D.
Mitchell Thomas G.
Rohrer Norman J.
Rose Ronald D.
Dinh Paul
LeStrange, Esq Michael J.
Parihar Suchin
Scully , Scott, Murphy & Presser, P.C.
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