Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2001-11-30
2003-04-22
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S618000, C438S675000, C438S740000, C438S763000
Reexamination Certificate
active
06551901
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the manufacture of semiconductor devices. More specifically, the invention relates to the prevention of contact to well leakage in semiconductor devices.
BACKGROUND OF THE INVENTION
High Density Plasma (HDP) oxide film is used to fill shallow trenches to isolate different transistor regions. The isolation HDP oxide filled regions are referred to as Field Oxide (FOX) for providing Shallow Trench Isolation (STI). To facilitate understanding,
FIG. 1
is a flow chart of a prior art process of manufacturing on a semiconductor chip formed by at least one semiconductor device with a borderless contact using STI on a substrate. When the space between a contact edge and an active area edge is reduced to zero by design, these contacts are called borderless contacts and local interconnect.
FIG. 2
is a schematic cross-sectional view of part of a substrate
204
of a semiconductor chip with field oxides
208
formed to provide Shallow Trench Isolation (STI). A nitride layer
212
is placed over the substrate
204
to provide an etch stop. An oxide layer
216
is placed between the nitride layer
212
and the substrate
204
to prevent damage to the substrate
204
by the nitride layer
212
. Such protective oxide layers may be called “pad oxide layers.” Generally, a field oxide is deposited and then a Chemical Mechanical Polishing (CMP) is used to polish the surface so that excess FOX is removed, providing a flat surface as shown, using the nitride layer
212
as a stop for the polishing (step
104
). The final height of the FOX may be >1000 Å above the substrate surface.
The nitride layer may then be etched away (step
108
). Phosphoric acid may be used to remove the nitride layer. Such a wet etching may have a high selectivity between the nitride layer
212
, the oxide layer
216
, and the FOX
208
.
FIG. 3
is an illustration of the substrate in
FIG. 2
after the nitride layer has been etch away. Due to the high selectivity, minimal amounts of oxide may be removed, providing negative angles
304
at the top of the FOX
208
. A Hydrogen Fluoride (HF) wet etch may be used to remove the oxide layer
216
, reduce the height of the FOX
208
, and change the angle of the FOX
208
at a transistor active edge, by establishing a positive slope
404
, as shown in
FIG. 4
(step
112
). The HF etch effectively moves the edges of the FOX back away from the transistor region.
A semiconductor device may be formed in the transistor region
408
between the FOXs
208
(step
116
). An example of such a semiconductor device is illustrated in FIG.
5
. In this example, the semiconductor device
504
comprises a source and a drain
508
, a gate oxide
516
, a polysilicon gate
520
, and metal silicides
524
for forming electrical contacts. The process of forming the semiconductor device may expose the FOX
208
to as many as ten wet etches, which may etch away part of the FOX
208
to the point of the top of the FOX
208
that is in contact with the implant areas forming the source and drain
508
. Such etchings may cause the edge between the FOX and the transistor to recess as much as 1100 Å.
A Nitride (SiN) layer
530
may be placed over the semiconductor device
504
and substrate
204
, forming an etch stop barrier layer and spacers on the sides of the polysilicon gate
520
(step
120
). An Inter-Level Dielectric (ILD) layer
540
may be placed over the nitride layer
530
(step
124
).
An electrically conductive contact
604
may then be formed in the ILD layer
540
, as shown in
FIG. 6
(step
128
). To form the contact
604
, a trench may be etched in the ILD layer
540
and through the nitride layer
530
. Such an etch may further etch the FOX
208
.
To reduce Integrated Circuit (IC) sizes, current device designs may provide the placement of contacts that may be coincident with the edge of the transistor active region, so that part of the contact may be above the FOX, as shown in FIG.
6
. If the FOX
208
has been etched too far, the contact
604
may come into contact with the well region of the substrate
204
, which is the region of the substrate below the source or drain
508
. Contact between the electrical contact
604
and the well region may cause a short to the well region, which may cause junction leakage.
The amount of FOX loss and recess may be enhanced with a PreGate Nitrogen Implant (PGNI), which may cause the FOX level to be below the transistor junction, causing a short to the well or ground. In addition, the variation in an ILD stack, consisting of both a layer of phosphorus oxide and silicon nitride, combined with plasma etch selectivity on both the type of the feature to be etched and the pattern density of features on a wafer, may result in longer etch time and a higher over etch percentage, to insure that all features are open to the transistor region. This higher percentage of contact (or LI Local Interconnect) over etch may punch deep into the field oxide, causing the final electrical connecting plug to make contact with the well region beneath the junction, causing a short to the wells. The variation of ILD thickness may also be dependent on polysilicon gate density. For ASIC devices, the polysilicon gate density may vary with different devices, making it hard to control ILD thickness, adding to the above-mentioned variation in an ILD stack.
In addition, there may be limitations on the selectivity between PSG and SiN during a PSG etch. There may also be limitations on the selectivity between SiN and FOX during an SiN etch.
It would be desirable to prevent contact between an electrical contact and the well region.
SUMMARY OF THE INVENTION
To achieve the foregoing and in accordance with the purpose of the present invention, a method of forming a semiconductor chip is provided. Generally, shallow trenches containing field oxide are provided on a substrate. At least one semiconductor device is formed between the shallow trenches. An oxide layer is formed over the at least one semiconductor device and the field oxide. An etch stop layer is formed over the oxide layer. An inter layer dielectric layer is formed over the etch stop layer. At least one contact hole is etched through the inter layer dielectric layer, the etch stop layer and at least partially through the oxide layer. The at least one contact hole is filled with a conductive material.
In addition, an inventive semiconductor chip is provided. Generally, shallow trenches containing field oxide are provided on a substrate. At least one semiconductor device is formed between the shallow trenches. An oxide layer is formed over the at least one semiconductor device and the field oxide. An etch stop layer is formed over the oxide layer. An inter layer dielectric layer is formed over the etch stop layer. At least one contact hole is etched through the inter layer dielectric layer, the etch stop layer and at least partially through the oxide layer. The at least one contact hole is filled with a conductive material.
These and other features of the present invention will be described in more detail below in the detailed description of the invention and in conjunction with the following figures.
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Allman Derryl J.
Gu Shiqun
McGrath Peter
Beyer Weaver & Thomas LLP
Jr. Carl Whitehead
LSI Logic Corporation
Smoot Stephen W.
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