Method for preventing backside polysilicon peeling in a 4T+2R SR

Details Method for preventing backside polysilicon peeling in a 4T+2R SR Method for preventing backside polysilicon peeling in a 4T+2R SR

1997-05-21

2000-01-25

Bowers, Charles

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

438778, 438238, 438384, 438385, 438928, 438488, 257903, 257904, H01L 21322

Patent

active

060178280

ABSTRACT:
The present invention is a method for preventing backside polysilicon peeling in 4T+2R SRAM process. This invention utilizes forming oxide cap layer on the backside of the wafer to protect the backside polysilicon. Thus, the backside polysilicon is free from peeling and damage.

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Stanley Wolf, Silcion processing for the VLSI Era, vol. 1, pp. 175, 170, 1990.

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