Method for preparing a semiconductor device

Details Method for preparing a semiconductor device Method for preparing a semiconductor device

1997-08-07

2001-02-27

Gulakowski, Randy (Department: 1746)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S704000, C438S724000, C438S744000, C438S756000, C438S757000, C438S763000, C216S047000, C216S057000, C216S079000, C216S099000

Reexamination Certificate

active

06194320

ABSTRACT:

The present invention relates to a method for preparing a semiconductor device, comprising sequentially depositing a silicon oxide film and a silicon nitride film on a semiconductor substrate and patterning the films.
In
FIGS. 9-14
, there is shown a cross-sectional view of a conventional method for preparing a semiconductor device, which has been disclosed in e.g. JP-A-7-193145. A semiconductor device is generally constituted by a memory cell region for forming memory cells and a peripheral region for forming peripheral circuits. The peripheral region is shown on the left side in the respective figures, and the memory cell region is shown on the right side in the respective figures. Now, the conventional method for preparing a semiconductor device will be described in reference to the respective figures.
First, a silicon oxide film
2
having a thickness of 300 angstrom is deposited on a silicon substrate. A silicon nitride film
3
having a thickness of 500 angstrom is deposited on the silicon oxide film
2
by a low pressure CVD (Chemical Vapor Deposition) method. A resist
4
which is patterned so as to expose only an n-type well forming region is formed on the silicon nitride film
3
. The silicon nitride film
3
is etched by dry-etching with a gas of CHF
3
/CF
4
/Ar=10/70/800, a pressure of 500 mTorr, an output of 500 W and a time period of 20 sec, the resist
4
serving as a mask. The silicon substrate
1
has phosphorus (P) put thereinto by ion implantation, the resist
4
serving as a mask (FIG.
9
(
a
)).
Next, the resist
4
is removed, and an oxide film
5
having a thickness of 5000 angstrom is formed, the silicon nitride film
3
serving as a mask. The silicon nitride film
3
is removed by hot phosphoric acid. A p-type well forming region has boron (B) put thereinto by ion implantation, the oxide film
5
serving as a mask (FIG.
9
(
b
)). The impurity which is doped in the silicon substrate
1
is thermally diffused to form n-type wells
6
and p-type wells
7
(FIG.
9
(
c
)).
Next, the oxide film
5
and the oxide film
2
are removed with hydrofluoric acid. A silicon oxide film
8
having a thickness of 300 angstrom, a polysilicon film
9
having a thickness of 1000 angstrom and a silicon nitride film
10
having a thickness of 2000 angstrom are sequentially deposited on the silicon substrate
1
. A resist
11
which is patterned so as to expose only field oxide forming regions as a separation insulating film is formed on the silicon nitride film
10
. Dry-etching with a gas of CHF
3
/CF
4
/Ar=10/70/800, a pressure of 500 mTorr, an output of 500 W and a time period of 30 sec is carried out, the oxide film
5
serving as a mask, to etch the silicon nitride film
10
(FIG.
9
(d)).
Next, a resist
12
which is patterned so as to expose only the p-type wells
7
in the field oxide forming regions is formed to cover the resist
11
. Ion implantation with boron (B) is carried out, the resist
12
and the resist
11
serving as a mask (FIG.
10
(
a
)). The resist
11
and the resist
12
are removed. Heat annealing is carried out, the silicon nitride film
10
serving as a mask, to form field oxides
13
having a thickness of 7000 angstrom. At that time, p
+
-channel stopper regions
14
are simultaneously formed (FIG.
10
(
b
)). (The p
+
-channel stopper regions
14
are omitted in the subsequent figures.)
Next, the silicon nitride film
10
is removed with hot phosphoric acid. Dry-etching with a gas of SF
6
=100 cc/min, a pressure of 600 mTorr, an output of 100 W and a time period of 35 sec is carried out to remove the polysilicon film
9
. Ion implantation with boron is carried out only in the memory cell region, a resist (not shown) serving as a mask, to control a threshold voltage of a memory transistor.
Next, the silicon oxide film
8
is removed with hydrofluoric acid. A silicon oxide film
15
having a thickness of 100 angstrom is formed on the silicon substrate
1
by a thermal oxidation method (FIG.
10
(
c
)). A polysilicon film
16
having a thickness of 1000 angstrom is deposited on the silicon oxide film
15
by a CVD method. A resist
17
which is patterned so as to cover the memory cell region is formed on the polysilicon film
16
. Dry-etching with a gas of Cl
2
/O
2
=36/4, a pressure of 5 mTorr, an output of 20 W and a time period of 41 sec is carried out to etch the polysilicon film
16
(FIG.
10
(
d
)). During this etching, the polysilicon film
16
is patterned in a cross-section different from the figure, i.e. in a cross-section taken along the line XIII—XIII of FIG.
10
(
d
). In
FIG. 13
, there is shown a cross-sectional view taken along the line XIII—XIII of FIG.
10
(
d
). The resist
17
is removed.
Next, a silicon oxide film
18
having a thickness of 60 angstrom is layered on the silicon substrate
1
by a CVD method. A silicon nitride film
19
having a thickness of 100 angstrom is layered on the silicon substrate
1
by a CVD method. A silicon oxide film
20
having a thickness of 60 angstrom is further layered on the silicon substrate
1
by a CVD method
FIG. 11. A
resist which is patterned so as to cover the memory cell region is formed on the silicon oxide film
20
.
Next, the substrate is immersed in a solution of HF (hydrofluoric acid) at 25° C. to carry out wet etching, the resist
21
serving as a mask, to etch the silicon oxide film
20
. A parallel plate etching system is used to carry out dry-etching with a gas of SF
6
/F
22
=48/12, a pressure of 275 mTorr, an output of 100 W, a time period of 18 sec, the resist
21
serving as a mask, to etch the silicon nitride film
19
. The substrate is immersed in a solution of HF (hydrofluoric acid) at 25° C., the resist serving as a mask, to carry out wet etching so as to etch the silicon oxide film
18
and the silicon oxide film
15
(FIG.
11
).
Next, the resist is removed, and an upper surface of the silicon substrate
1
is treated with hydrofluoric acid to remove a natural oxide film. A thermal oxidation film as a gate oxide is formed on the silicon substrate
1
by a thermal oxidation method (FIG.
11
). A polysilicon film having a thickness of 2000 angstrom is deposited on the thermal oxide film and the silicon oxide film
24
by a CVD method. A patterned resist
24
is formed on the polysilicon film. Dry-etching with a gas of Cl
2
/O
2
=36/4, a pressure of 5 mTorr, an output of 30 W and a time period of 60 sec is carried out, the resist serving as a mask, to etch the polysilicon film so as to form gate electrodes in the peripheral region.
Next, the resist is removed. A patterned resist is formed on the gate electrodes and the polysilicon film. Dry-etching with a gas of Cl
2
/O
2
=36/4, a pressure of 5 mTorr, an output of 30 W and a time period of 60 sec is carried out, the resist
26
serving as a mask, to etch the polysilicon film
23
. A dry-etching with a gas of CF
4
/Ar=70/800, a pressure of 700 mTorr, an output of 200 W and a time period of 20 sec is carried out to etch the silicon oxide film
20
, the silicon nitride film
19
and the silicon oxide film
18
. Dry-etching with a gas of Cl
2
/O
2
=36/4, a pressure of 5 mTorr, an output of 30 W and a time period of 60 sec is carried out to etch the polysilicon film
16
. As a result, control gates
27
and floating gates
28
are formed in the memory cell region to provide nonvolatile gate electrodes (FIG.
12
(
a
)). Obviously from
FIG. 14
showing a cross-sectional view taken along the line XVI—XVI of FIG.
12
(
a
), the floating gates
28
have sidewalls provided with the silicon oxide film
20
, the silicon nitride film
19
and the silicon oxide film
18
layered.
Next, the resist
26
is removed, and sidewall insulating films
29
, source/drain regions
30
in the memory cell region, source/drain regions
31
in the peripheral region, a silicon oxide film
32
, a silicon nitride film
33
, and a smooth coating film
34
are sequentially formed. Contact holes
35
are formed so as to reach surfaces of the respective source/drain regions

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