Method for precise architectural update in an out-of-order proce

Details Method for precise architectural update in an out-of-order proce Method for precise architectural update in an out-of-order proce

1997-06-25

1999-09-28

Pan, Daniel H.

Electrical computers and digital processing systems: processing

Processing control

Branching

712238, 711145, G06F 930, G06F 938

Patent

active

059580470

ABSTRACT:
A processor including at least one execution unit generating out-of-order results and out-of-order condition codes. Precise architectural state of the processor is maintained by providing a results buffer having a number of slots and providing a condition code buffer having the same number of slots as the results buffer, each slot in the condition code buffer in one-to-one correspondence with a slot in the results buffer. Each live instruction in the processor is assigned a slot in the results buffer and the condition code buffer. Each speculative result produced by the execution units is stored in the assigned slot in the results buffer. When an instruction is retired, the results for that instruction are transferred to an architectural result register and any condition codes generated by that instruction are transferred to an architectural condition code register.

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