Electrical computers and digital data processing systems: input/ – Intrasystem connection
Reexamination Certificate
2000-05-30
2003-09-16
Thai, Xuan M. (Department: 2189)
Electrical computers and digital data processing systems: input/
Intrasystem connection
C710S305000
Reexamination Certificate
active
06622187
ABSTRACT:
The present invention relates to a method for pre-processing data packets in a bus interface unit received via a communication bus and bus interface unit for use within this method as well as an application data processing unit for use within this method.
BACKGROUND OF THE INVENTION
A high sophistic communication bus is the IEEE1394 bus which is a low cost, high performance serial bus. It has a read/write memory architecture and a highly sophisticated communication protocol. Data rates of 100, 200 or 400 Mbit/s can be transmitted in nearly real time. Simultaneously, data can be transmitted bi-directionally. The first ten bits of transmitted address values refer to one of up to 1023 possible IEEE1394 bus clusters. The following six bits of the transmitted address values refer within a specific cluster to one of up to 63 nodes to which an application or device is assigned. Data between nodes can be exchanged without interaction of a host controller. Devices can be connected to or disrupted from the network at any time, allowing a plug and play behaviour.
The communication protocol has three layers: physical layer, data link layer, and transaction layer. Typically, the transaction layer is realised by firmware which means by software within an application data processing unit or control processor of a bus station whereas the other layers are implemented in the bus interface unit using chip sets.
The physical layer contains analogue transceivers and a digital state machine. It handles bus auto-configuration and hot plug. It reclocks, regenerates and repeats all packets and forwards all data packets to the local data link layer. It carries out-packet framing, for example speed code, prefix, and packet end assembling. It arbitrates and transmits packets from the local link layer. Available IC types are e.g. TSB11C01, TSB11LV01, TSB21LV03, and TSB41LV03 of Texas Instruments, MB86611 of Fujitsu, and 21S750 of IBM.
The data link layer performs all steps for distributing data packets to its destination. It recognises packets addressed to the node by address recognition and decodes the packet headers. It delivers packets to higher layers and generates packets from higher layers. It works either isochronous for AV data use or asynchronous for control data use.
In the isochronous mode a channel having a guaranteed bandwidth is established. There is a defined latency. The transmission is performed in 125 &mgr;s time slots or cycles. This mode has a higher priority than the asynchronous data transfer mode.
The asynchronous mode is not time critical, but safe. It operates as an acknowledged service with a busy and retry protocol. Fixed addresses are used. Transmission takes place when the bus is idle. The asynchronous mode handles read request/response, write request/response, and lock request/response. It performs cycle control, CRC generation and validation. Available data link layer IC types are e.g. TSB12C01A, TSB12LV21, TSB12LV31, and TSB12LV41 of Texas Instruments, and PDI1394L11 of Philips.
The transaction layer implements asynchronous bus transactions:
Read request/read response
Write request/write response
Lock request/lock response.
As mentioned above it can be implemented by software running on a microcontroller, such as e.g. the i960 of SparcLite. There may also be an AV (audio video) layer carrying out device control, connection management, timestamping, and packetising.
In IEEE1394 systems, the data link layer acts as an interface between an external application and the IEEE1394 bus (through the physical layer). The external application can be for example a consumer electronics device, such as a set-top-box or a VCR or a DVD player, which delivers/receives latency critical isochronous data and non-latency critical asynchronous data. Here, the asynchronous data packets are used for the controlling operations or register read/write/lock operations. Isochronous data packets contain information items like video-/audio data. The external application could also be a personal computer related device such as a Hard Disk Drive which delivers and receives asynchronous data packets only. Here, asynchronous data packets may include all kind of data inclusive audio/video data.
In IEEE1394 bus standard it is defined that the data packets are arranged in quadlets (one quadlet consists of four bytes corresponding to 32 Bit). It is also defined in this standard that the bus interface unit itself has to be of the big endian type which means that the byte order within a quadlet is so, that the most significant byte is stored in the lowest address, etc. A more detailed definition of this expression will be presented later on in the specification. There are two types of byte ordering schemes known from computer technology. One is the big endian type and the other is the little endian type. In little endian type microprocessors the bytes of a multi byte data word are stored from the little end on, i.e. the least significant byte is stored in the lowest address and so on. Both types are very often used in microelectronics. There are microcontrollers or microprocessors of either the big or little endian type available. When designing a bus station with IEEE1394 bus interface, the problem arises to arrange the byte-order of quadlets in the asynchronous data packet header in accordance to the target microcontroller's byte order because this header data has to be evaluated in the target microcontroller as the header data evaluation belongs to the transaction layer. One solution could be to do the byte reordering by software in the target microcontroller after reading the data from the bus interface unit. This solution has however the disadvantage that the target microcontroller has to include a byte reordering task if it is of little endian type which leads to a loss of performance on the target microcontroller site.
SUMMARY OF THE INVENTION
After recognising this disadvantage the invention consists first in the idea of doing the byte-order change of the header quadlets of the asynchronous data packets within the data link layer unit in hardware depending on an information item which clarifies whether the application data processing unit is of big or little endian type.
In case, where the data link layer unit has a register file with a number of registers having multi-byte data word entries, this solution has the disadvantage, that also the bytes of the entries in these registers need to be reordered when interpreted in a control processor if the control processor is of a different type as the link layer unit.
The invention therefore consists also in the second idea of doing a byte order change of the payload data field instead of changing the byte order in the header data field. By doing so, the multiplexing device for the byte reordering can be very simple because the controlling of the multiplexer need not to take into account other data components like register file entries.
Both solutions have the advantage that no processing power of the application data processing unit is required for byte reordering. Also, the software of the application data processing unit is simplified.
Advantageously, additional embodiments of the inventive method are disclosed in the respective dependent claims.
E.g. it is advantageous when the step of reordering the bytes of the payload data field is accompanied by a further reordering of the bytes in the header data field and the payload data field as claimed in claim 2. This can be done with another multiplexing device or very simply by making permanent hardwired cross connections in the data bus which transfers the data packet from the interface unit (
20
) to a memory (
33
) for the application data processing unit (
30
).
Writing the information item which clarifies whether the application data processing unit is of big or little endian type into the bus interface unit during initialisation according to claim 4 is an advantageous embodiment because during initialisation a lot of parameters have to be set within the bus interface unit anyway and the entry does not
Brune Thomas
Cahnbley Jens
Ostermann Ralf
Schweidler Siegfried
Kiel Paul P.
Thai Xuan M.
Thomson Licensing S.A.
Tripoli Joseph S.
Vo Tim
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