Method for power management for computer system

Details Method for power management for computer system Method for power management for computer system

2008-11-21

2011-11-01

Butler, Dennis M (Department: 2115)

Electrical computers and digital processing systems: support

Computer power control

Having power source monitoring

C713S300000, C713S310000

Reexamination Certificate

active

08051319

ABSTRACT:
The invention provides a method for power management for a computer system. In one embodiment, the computer system comprises a system controller, a chipset, and a battery coupled to the chipset via a system management bus. First, a timer of the chipset is used to calculate an accumulated time value. When the accumulated time value exceeds a threshold value, the chipset is directed to send a system control interrupt to the system controller. After the system controller receives the system control interrupt, the system controller is triggered to detect a power level supplied by the battery via the system management bus.

REFERENCES:
patent: 7574321 (2009-08-01), Kernahan et al.
patent: 2001/0032321 (2001-10-01), Nanno et al.
patent: 1622005 (2005-06-01), None
English abstract of CN1622005, pub. Jun. 1, 2005.

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