Method for post-routing redundant via insertion in...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000

Reexamination Certificate

active

11391628

ABSTRACT:
The objective of the invention is to provide a method for post-routing redundant via insertion. The method is to construct a conflict graph from a post-routing design first, to find a maximal independent set (MIS) of the conflict graph, and to replace a single via with a double via for each vertex in the maximal independent set. Furthermore, since redundant vias can be classified into on-track and off-track ones and since on-track ones have better electrical properties, the invention also presents two methods to increase the amount of on-track redundant vias while a redundant via insertion solution is given.

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