Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-09-20
2005-09-20
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06948138
ABSTRACT:
A method for use by a placement and routing tool automatically selects positions for all n I/O buffers of an IC from among a set of m available legal positions for such buffers within an IC layout so as to best meet a set of criteria affected by I/O buffer placement. The method initially establishes a weighted cost function ci,jquantifying a cost, relative to that set of criteria, of assigning the ithI/O buffer to the jthlegal position. The weighted cost function is then evaluated with respect to each possible combination of i and j to produce an m×n cost data matrix indicating all costs associated with all of the m×n possible I/O buffer placements. The cost data matrix is then analyzed to produce a placement plan assigning each I/O buffer to a separate legal position in a way that minimizes a total cost of the buffer placement with respect to the set of criteria. The method may also be used to assign I/O pads among a set of legal pad positions.
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Bedell Daniel J.
Cadence Design Systems Inc.
Garbowski Leigh M.
Smith-Hill and Bedell
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