Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
1997-10-27
2001-01-16
Mills, Gregory (Department: 1763)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S694000, C216S079000
Reexamination Certificate
active
06174815
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for planarizing dynamic random access memory (DRAM). More particularly, the present invention relates to a method for planarizing DRAM cells.
2. Description of Related Art
In the manufacture of sub-micron very large scale integrated (VLSI) circuits or ultra large scale integrated (ULSI) circuits, planarization is a very important process. DRAM is a very common and widely used memory.
FIGS. 1A through 1C
are cross-sectional views showing the progression of manufacturing steps in the planarization of a DRAM cell by a conventional method. First, as shown in
FIG. 1A
, a silicon substrate
10
having a memory cell circuit region formed thereon is provided. The memory cell circuit region includes a field oxide layer
11
, an oxide layer
12
and a capacitor
13
.
Next, as shown in
FIG. 1B
, an insulating layer
14
is deposited over the silicon substrate and the memory cell circuit region.
In a conventional method for forming DRAM cells, since the capacitor
13
is formed above the memory cell circuit region, there will be a height difference between the top of the capacitor
13
and the surrounding memory cell circuit region. In the planarization of sub-half-micron integrated circuits, if the step height hc (shown in
FIG. 1A
) of a capacitor
13
is bigger than or equal to about 0.5 &mgr;m, planarization becomes difficult, and may lead to poor structural quality in subsequent processes.
Next, for example, as shown in
FIG. 1C
, a subsequent metallization process is performed. In the metallization process, a photoresist layer is formed over the insulating layer
14
, then light is shone onto the photoresist layer through a photomask having a desired pattern for forming conducting wires
15
and
16
. Since the photoresist layer will react chemically when exposed to light, after development with chemicals, the desired etching pattern is formed. However, as mentioned before, because the difference in height between the top of the capacitor and its surrounding areas is big, there will be insufficient depth of focus during light exposure which may lead to defocusing. Therefore, pattern on the photoresist layer will be properly transferred and may ultimately lead to the deformation of conducting wires after the metallic etching operation. As a result, the resistance of a conductive wire such as
15
becomes larger.
To solve the problems caused by a difference in height levels, a chemical-mechanical polishing operation is generally applied. The chemical-mechanical polishing method is a global planarization method. Principly, the chemical-mechanical polishing method combines mechanical polishing with suitable chemical reagents, a slurry which is a mixture of colloidal silica and potassium hydroxide (KOH), and operates under a suitably controlled set of parameters to obtain an optimal planarity. The set of controlling parameters includes: slurry composition, magnitude of pressure on the wafer, rotational speed of the polishing head, material of the polishing pad, size distribution of polishing particles, working temperature, pH and so on. In general, all these parameters need to be changed according to the kind of material to be polished. Hence, chemical-mechanical polishing is a hard to control, costly and time consuming global planarization process. In light of the foregoing, there is a need in the art to improve the planarization method.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to provide a method for planarizing DRAM cells that solve the problems caused by difference in height levels within the memory cell circuit regions, and ensure a consistant quality in subsequent processes.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention includes a method for planarizing DRAM cells comprising the steps of providing a silicon substrate having a semiconductor component, a field oxide layer, an oxide layer and a capacitor formed thereon; forming a first dielectric layer over the substrate; etching back portions of the first dielectric layer to form a spacer layer; forming a second dielectric layer over the spacer layer; forming an insulating layer over the second dielectric layer; and fully etching back the insulating layer, and etching back portions of the second dielectric layer to form a third dielectric layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5324683 (1994-06-01), Fitch et al.
patent: 5576928 (1996-11-01), Summerfelt et al.
patent: 5847464 (1998-12-01), Singh et al.
patent: 5872056 (1999-02-01), Manning
Kuo Chau-Jen
Liu Bin
Yang Fu-Liang
Mills Gregory
Powell Alva C.
Rabin & Champagne, P.C.
Vanguard Semiconductor Corp.
LandOfFree
Method for planarizing DRAM cells does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for planarizing DRAM cells, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for planarizing DRAM cells will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2551764