Method for planarizing an insulating layer

Adhesive bonding and miscellaneous chemical manufacture – Delaminating processes adapted for specified product – Delaminating in preparation for post processing recycling step

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156647, 156649, 156653, 156657, 156662, 20419232, 20419237, B44C 122, C03C 1500

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active

049522744

ABSTRACT:
In a method for planarizing an insulating layer, the height of steps in a layer of insulating material are reduced while tapering side walls of the steps by forming a layer of sacrificial material between the steps and etching the insulating material and the sacrificial material in a low pressure plasma comprising reactive ions and facetting ions. This method combines many of the advantages of Resist Etch Back (REB) and argon facetting techniques while reducing the deleterious effects of macroloading and microloading.

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Y. Hazuki et al., A New Application of Rie to Planarization and Edge Rounding of SiO.sub.2 Hole in the A1 Multilevel Interconnection, VLSI Sep. 82.
Tom Abraham, Reactive Facet Tapering of Plasma Oxide for Multilevel Interconnect Applications, V-MIC Conf. Jun. 87.
E. J. McInerney, AN IN-SITU Planarized PECVD Silicon Dioxide Interlayer Dielectric, V-MIC Conf., Jun. 86.
G. E. Gimpelson et al., Plasma Planarization with a Non-Planar Sacrificial Layer, V-MIC Conf., Jun. 84.
T. Abraham, Sidewall Tapering of Plasma Etched Metal Interconnects, V-MIC Conf., Jun. 86.
Barbara Vasquez, Planarized Oxide with Sacrificial Photoresist: Etch Rate Sensitivity to Pattern Density, V-MIS Conf., Jun. 87.
H. Kotami et al., Sputter-Etching Planarization for Multilevel Metallization, J. Electrochem. Soc., p. 645, Mar. 1983.

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