Method for planarizing a semiconductor layer

Details Method for planarizing a semiconductor layer Method for planarizing a semiconductor layer

1996-02-20

1998-03-17

Chapman, Mark

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Making electrical device

1566451, 216 38, 438692, 438697, 438699, 438703, 438759, 438761, G03C 500

Patent

active

057285071

ABSTRACT:
A moat pattern (19) is formed in a first layer of material (11) to improve the profile of a planarization process. The presence of the moat pattern (19) in the periphery of a semiconductor substrate (10,30) moves the effects of the relaxation distance (13) away from the critical areas of the semiconductor substrate (30). The moat pattern (19) is formed during a photolithographic process by using a photolithographic mask (20) that has a portion (22) that defines and patterns the moat pattern (19). The moat pattern (19) is defined as edge dice (31) are patterned across the semiconductor substrate (30).

REFERENCES:
patent: 5627110 (1997-05-01), Lee et al.
patent: 5629242 (1997-05-01), Nagashima et al.
J. Warnock; "A Two-Dimensional process Model for Chemimechanical Polish Planarization;".
J. Electrochem. Soc.; vol. 138, No. 8, pp. 2398-2402 (Aug. 1991).
S. Sivaram, et al.; "Planarizing Interlevel Dielectrics by Chemical-Mechanical Polishing;" Solid State Technology, pp. 87-91 (May 1992).

Affiliated with

Also associated with

Rating

Method for planarizing a semiconductor layer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for planarizing a semiconductor layer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for planarizing a semiconductor layer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-956280