Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-02-14
2002-04-30
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S697000
Reexamination Certificate
active
06380068
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates to a planarization method. More particularly, the present invention relates to a planarization method for flash memory devices.
2. Description of Related Art
Flash memory device is an electrically-erasable-programmable-read-only memory device, which has the advantages of being programmable, erasable and the ability of retaining data after the power is off. A flash memory device is thus commonly used in personal computer and electronic devices. Flash memory device is also a non-volatile memory (NVM), which has the advantages of being small in dimension, speedy data retrieval and storage, and low power consumption. Furthermore, the erasing of data in a flash memory device uses the “block-by-block” method; therefore, it also has the advantage of having faster operational speed.
The basic structure of the memory cell region of a flash memory device includes a stacked gate structure, wherein the stacked gate structure comprises a tunnel oxide layer, a floating gate, a dielectric layer, a control gate and source/drain regions in the substrate on both sides of the stacked gate structure. In addition, at the peripheral of the memory cell region is the periphery circuit region, which includes peripheral devices that are used to write, to erase or to read data in the memory cell region.
The conventional fabrication method of a flash memory device includes depositing a dielectric layer on the substrate to cover the memory cell region and the peripheral circuit region after forming the memory cell region and the peripheral circuit region at the peripheral of the memory cell region. Chemical-mechanical polishing (CMP) is then conducted to form a planarized surface.
Using the conventional CMP process to planarize a flash memory device has several disadvantages. First of all, chemical-mechanical polishing a larger area is easier to control, for example, the area of the peripheral circuit region. However, chemical-mechanical polishing a smaller area, for example, the area of the memory cell region, is difficult to control. Hence, using chemical-mechanical polishing for planarization, it is difficult to control the polishing end point for the entire device. In addition, microscratches are easily induced on the device. Moreover, using chemical mechanical polishing to planarize an area with uneven surface levels, for example, the shallow trench isolation region, would easily have the polished debris remaining in the area.
SUMMARY OF THE INVENTION
The invention provides a method to planarize the flash memory device. The method does not require the application of chemical-mechanical polishing to accomplish the planarization of the flash memory device. The various disadvantages of chemical-mechanical polishing are thus prevented.
The present invention provides a planarization method for a flash memory device, wherein this method includes forming sequentially a polysilicon layer and a cap layer on a substrate. Thereafter, the cap layer and the polysilicon layer are patterned to form the peripheral circuit region and the memory cell region. A dielectric layer is then formed the cap layer and then etched to expose a part of the cap layer, such that the dielectric layer above the cap layer and the dielectric layer on both sides of the cap layer becomes separated. A portion of the dielectric layer in the peripheral circuit region is further removed. Subsequently the cap layer is removed and concurrently removed the dielectric layer above the cap layer to complete the planazation of the flash memory device.
According to the present invention, the planarization of a flash memory device is accomplished by etching. The common problem, encountered in chemical-mechanical polishing, such as controlling the polishing end point, is prevented.
The present invention employs the etching technique to accomplish the planarization of a flash memory device. The common problem, such as having polished debris remaining in areas with uneven surface levels, is prevented
The present invention employs the etching technique to accomplish the planarization of a flash memory device. The common problem, such as forming microscratches and damaging the polished surface, is prevented.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5272117 (1993-12-01), Roth et al.
patent: 5789314 (1998-08-01), Yen et al.
patent: 6027950 (2000-02-01), Harvey et al.
patent: 6117760 (2000-09-01), Gardner et al.
Jeng Pei-Ren
Wu Shu Li
Chaudhuri Olik
Macronix International Co. Ltd.
Patents J. C.
Pham Hoai
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