Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-12-17
2001-04-03
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S618000, C438S626000
Reexamination Certificate
active
06211060
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87113558, filed Aug. 18, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to a method for planarizing a damascene structure, and more particularly to a planarization method with the combination of an electrical polishing method and a chemical mechanical polishing method to decrease the occurrence of dishing and erosion effects.
2. Background
As the level of integration for integrated circuits increases, the amount of yield, cost and reliability necessary for semiconductor devices increases, too. Damascene processing method is invented due to these requirements. The method is capable of applying to the manufacturing processes of interconnect, via opening and contact opening to displace the conventional metal process, such as using a reactive ion etching method to etch CMOS and logic memory.
FIGS. 1A
to
1
B are cross-sectional views showing the conventional planarization steps of a damascene structure.
As shown in
FIG. 1A
, using a step of photolithography and etching with the etching time controlled, a trench
14
is formed on the dielectric layer
10
. A metal layer
12
is then formed on the dielectric layer and fills the trench
14
.
As shown in
FIG. 1B
, a chemical mechanical polishing method is used for polishing wafer to remain the metal layer
12
within the trench
14
. The dielectric layer
10
is utilized as a polishing stop layer during the polishing step by using slurry having high polish selectivity to the metal layer
12
.
The key point of damascence process is the optimization of the chemical mechanical polishing process, especially when the thickness and flatness of the metal layer are controlled by the chemical mechanical polishing process. Dishing effect is occurred on the conductive material layer, for example, tungsten metal, during the chemical mechanical polishing process. Moreover, step height effect is occurred after the depositing step of the conductive material over the dielectric layer and the trench. That is, the height of the conductive layer, for example, metal layer, deposited over the trench is lower than that of the conductive layer deposited over the dielectric layer.
Slurry is composed of polishing particles and chemical enhance reagents. Some particles are deposited on the dishing portions of the metal layer. The polishing speed of the dishing portions are higher than that of other portions, hence the dishing effect become more seriously. Further, additional polishing, for example, over-polishing, is needed after the dielectric layer is exposed to ensure the metal layer over the dielectric layer is removed. Therefore, the metal layer is further polished and dishing effect is occurred.
Erosion effect is another problem of the chemical mechanical polishing process. If there are no enough oxide material used as a stop layer, the erosion effect is occurred. As the polishing process goes on, the oxide layer becomes much thinner. Therefore, the conductive material layer formed under the stop layer is over polished. It makes the thickness of the conductive material layer not enough. Erosion effect is easily occurred, especially on the conductive material layer having high integration and scantily oxide layer formed thereon.
This operation is carried out under suitable controlling parameter settings to obtain the best planarity. However, the list of controlling parameters is long and includes the composition of the slurry, the pressure exerted on the silicon wafer, the rotating speed and composition of the polishing pad, as well as the distribution, temperature, and pH of the polishing particles.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method for planarizing damascence structure. In the damascence planarizing process according to the invention, the disadvantages of the conventional process are improved.
To achieve these objects and advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed towards a damascence planarizing process. A dielectric layer is deposited over the wafer. A trench is then formed by defining the dielectric layer. Thereafter, a metal layer is deposited over the dielectric layer and fills the trench. An electrical polishing and a chemical mechanical polishing step are performed to remove the metal layer until the dielectric layer is exposed.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.
REFERENCES:
patent: 5256565 (1993-10-01), Bernhardt et al.
patent: 5516729 (1996-05-01), Dawson
patent: 5663102 (1997-09-01), Park
Lin Tsang-Jung
Lu Tsung-Lin
Huang Jiawei
J. C. Patents
Lytle Craig P
Smith Matthew
United Microelectronics Corp.
LandOfFree
Method for planarizing a damascene structure does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for planarizing a damascene structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for planarizing a damascene structure will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2437916